| Xeon Central processing unit |
|
| Produced: | From 1998 to present |
| Manufacturer: | Intel |
| Max CPU clock: | 400 MHz to 3. The hertz (symbol Hz) is a measure of Frequency, informally defined as the number of events occurring per Second. 73 GHz |
| FSB speeds: | 100 MHz to 1. The hertz (symbol Hz) is a measure of Frequency, informally defined as the number of events occurring per Second. In Personal computers the Front Side Bus ( FSB) is the bus that carries data between the CPU and the northbridge. The hertz (symbol Hz) is a measure of Frequency, informally defined as the number of events occurring per Second. 6 GHz |
| Instruction set: | x86 |
| Microarchitecture: | Intel Core Microarchitecture, NetBurst, P6 |
| Cores: | 1, 2, or 4 |
The Xeon brand refers to many families of Intel's x86 multiprocessing CPUs – for dual-processor (DP) and multi-processor (MP) configuration on a single motherboard targeted at non-consumer markets of server and workstation computers, and also at blade servers and embedded systems. The hertz (symbol Hz) is a measure of Frequency, informally defined as the number of events occurring per Second. An instruction set is a list of all the instructions and all their variations that a processor can execute See also X86 assembly language The generic term x86 refers to the most commercially successful Instruction set architecture in the history of Personal In Computer engineering, microarchitecture (sometime abbreviated to µarch or uarch is a description of the Electrical circuitry of a Computer, Central A multi-core processor (or chip-level multiprocessor, CMP) combines two or more independent cores into a single package composed of a single Integrated See also X86 assembly language The generic term x86 refers to the most commercially successful Instruction set architecture in the history of Personal Multiprocessing is the use of two or more central processing units (CPUs within a single computer system A motherboard is the central or primary Printed circuit board (PCB making up a complex electronic system such as a modern Computer or Laptop A workstation, such as a Unix workstation, RISC workstation or Engineering workstation, is a high-end Microcomputer Blade servers are self-contained/ all inclusive computer servers, designed for high density An embedded system is a special-purpose Computer system designed to perform one or a few dedicated functions often with Real-time computing constraints The Xeon brand has been maintained over several generations of x86 and x86-64 processors. x86-64 is a Superset of the x86 instruction set architecture. Older models added the Xeon moniker to the end of the name of their corresponding desktop processor, but more recent models used the name Xeon on its own. The Xeon CPUs generally have more cache than their desktop counterparts in addition to multiprocessing capabilities. In Computer science, a cache (kæʃ like "cash") is a collection of data duplicating original Multiprocessing is the use of two or more central processing units (CPUs within a single computer system Intel's (non-x86) IA-64 processors are called Itanium, not Xeon. Itanium is the brand name for 64-bit Intel Microprocessors that implement the Intel Itanium architecture (formerly called IA-64) Itanium is the brand name for 64-bit Intel Microprocessors that implement the Intel Itanium architecture (formerly called IA-64)
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The first Xeon branded processor was released in 1998, named the Pentium II Xeon (codenamed "Drake"), as the replacement of the Pentium Pro. Year 1998 ( MCMXCVIII) was a Common year starting on Thursday (link will display full 1998 Gregorian calendar) The Pentium II brand refers to Intel 's sixth-generation Microarchitecture (" Intel P6 " and x86 -compatible Microprocessors The Pentium Pro is a sixth-generation X86 -based Microprocessor developed and manufactured by Intel introduced in November 1995 It was based on the 0. 25 µm "Deschutes" core (P6 microarchitecture) branded Pentium II (sharing its 80523 product code), used either a 440GX (a dual-processor workstation chipset) or 450NX (quad-processor, or oct with additional logic) chipset, and differed from the Pentium II desktop CPU (Deschutes) in that its off-die L2 cache ran at full speed. The Pentium II brand refers to Intel 's sixth-generation Microarchitecture (" Intel P6 " and x86 -compatible Microprocessors The P6 Microarchitecture is the sixth generation Intel X86 Microprocessor architecture released in 1995. A chipset is a group of Integrated circuits or chips that are designed to work together and are usually marketed as a single product It also used a larger slot known as slot 2. Slot 2 refers to the physical and electrical specification for the 330-lead edge-connector used by some of Intel 's Pentium II Xeon and certain models of the Cache sizes were 512 KB (512 KiB), 1 MB (1 MiB) and 2 MB, and it used a 100 MT/s front side bus (FSB). A kibibyte (a contraction of ki lo bi nary byte) is a unit of Information or Computer storage, established by the International A mebibyte (a contraction of me ga bi nary byte) is a unit of Information or Computer storage, abbreviated MiB. Gigatransfer (GT and Megatransfer (MT are terms used in computer technology referring to a number of data transfers (or operations In Personal computers the Front Side Bus ( FSB) is the bus that carries data between the CPU and the northbridge.
In 1999, the Pentium II Xeon was replaced by the Pentium III Xeon. Year 1999 ( MCMXCIX) was a Common year starting on Friday (link will display full 1999 Gregorian calendar) The Pentium II brand refers to Intel 's sixth-generation Microarchitecture (" Intel P6 " and x86 -compatible Microprocessors Pentium III variants Katmai The first Pentium III variant was the Katmai (Intel product code 80525 Reflecting the incremental changes from the Pentium II "Deschutes" core to the Pentium III "Katmai" core, the first Pentium III Xeon, named "Tanner", was just like its predecessor except for the addition of Streaming SIMD Extensions (SSE) and a few cache controller improvements. The Pentium II brand refers to Intel 's sixth-generation Microarchitecture (" Intel P6 " and x86 -compatible Microprocessors Pentium III variants Katmai The first Pentium III variant was the Katmai (Intel product code 80525 S treaming '''S'''IMD E xtensions ( SSE) is a SIMD (Single Instruction Multiple Data Instruction set extension to the X86 The second version, named "Cascades", was based on the Pentium III "Coppermine" core. Pentium III variants Katmai The first Pentium III variant was the Katmai (Intel product code 80525 The "Cascades" Xeon used a 133 MT/s bus and relatively small 256 KB on-die L2 cache resulting in almost the same capabilities as the Slot 1 Coppermine processors, which were capable of dual-processor operation but not quad-processor operation. Slot 1 refers to the physical and electrical specification for the connector used by some of Intel 's microprocessors including the Celeron, Pentium II To improve this situation, Intel released another version, officially also named "Cascades", but often referred to as "Cascades 2 MB". That came in two variants: with 1 MB or 2 MB of L2 cache. Its bus speed was fixed at 100 MT/s, though in practice the cache was able to offset this. Product codes for Tanner and Cascades mirrored that of Katmai and Coppermine; 80525 and 80526 respectively.
In mid-2001, the Xeon brand was introduced ("Pentium" was dropped from the name). The initial variant that used the new NetBurst architecture, "Foster", was slightly different from the desktop Pentium 4 ("Willamette"). The Intel NetBurst Microarchitecture, called P68 inside Intel was the successor to the P6 microarchitecture in the X86 family of CPUs The Pentium 4 brand refers to Intel 's line of single- core mainstream desktop and Laptop Central processing units (CPUs introduced The Pentium 4 brand refers to Intel 's line of single- core mainstream desktop and Laptop Central processing units (CPUs introduced It was a decent chip for workstations, but for server applications it was almost always outperformed by the older Cascades 2 MB core and AMD's Athlon MP. Athlon is the brand name applied to a series of different X86 processors designed and manufactured by AMD. Combined with the need to use expensive Rambus Dynamic RAM, the Foster's sales were somewhat unimpressive. Direct Rambus DRAM or DRDRAM (sometimes just called Rambus DRAM or RDRAM) is a type of synchronous dynamic RAM, designed by the Rambus
At most two Foster processors could be accommodated in an SMP system built with a mainstream chipset, so a second version (Foster MP) was introduced with a 1 MB L3 cache and the Jackson Hyper-Threading capacity. In Computing, symmetric multiprocessing or SMP involves a Multiprocessor computer-architecture where two or more identical processors can connect to a single Hyper-threading (officially termed Hyper-Threading Technology or HTT) is an Intel-proprietary technology This improved performance slightly, but not enough to lift it out of third place. It was also priced much higher than the dual-processor (DP) versions. The Foster shared the 80528 product code with Willamette.
| Model | Speed (GHz) | L2 Cache (MB) | FSB (MHz) | TDP (Watts) |
|---|---|---|---|---|
| 1. 4 | 56 | |||
| 1. 5 | 59. 2 | |||
| 1. 7 | 65. 8 | |||
| 2. 0 | 77. 5 |
In 2002 Intel released a 130 nm version of Xeon branded CPU, codenamed "Prestonia". See also 2002 (disambiguation Year 2002 ( MMII) was a Common year starting on Tuesday of the Gregorian calendar. It supported Intel's new Hyper-Threading technology and had a 512 KB L2 cache. This was based on the "Northwood" Pentium 4 core. The Pentium 4 brand refers to Intel 's line of single- core mainstream desktop and Laptop Central processing units (CPUs introduced A new server chipset, E7500 (which allowed the use of dual-channel DDR SDRAM) was released to support this processor in servers, and soon the bus speed was boosted to 533 MT/s (accompanied by new chipsets: the E7501 for servers and the E7505 for workstations). DDR SDRAM ( double data rate synchronous dynamic random access memory) is a class of memory Integrated circuit used in Computers It achieves nearly twice The Prestonia performed much better than its predecessor and noticeably better than Athlon MP. The support of new features in the E75xx series also gave it a key advantage over the Pentium III Xeon and Athlon MP branded CPUs (both stuck with rather old chipsets), and it quickly became the top-selling server/workstation processor.
Subsequent to the Prestonia was the "Gallatin", which had an L3 cache of 1 MB or 2 MB. Its Xeon MP version also performed much better than the Foster MP, and was popular in servers. Later experience with the 130 nm process allowed Intel to create the Xeon MP branded Gallatin with 4 MB cache. The Xeon branded Prestonia and Gallatin were designated 80532, like Northwood.
Due to a lack of success with Intel's Itanium and Itanium 2 processors, AMD was able to introduce x86-64, a 64-bit extension to the x86 architecture. x86-64 is a Superset of the x86 instruction set architecture. See also X86 assembly language The generic term x86 refers to the most commercially successful Instruction set architecture in the history of Personal Intel followed suit by including EM64T (almost identical) in the 90 nm version of the Pentium 4 ("Prescott"), and a Xeon version codenamed "Nocona" was released in 2004. x86-64 is a Superset of the x86 instruction set architecture. The 90 nanometer (90 nm process refers to the level of CMOS process technology that was reached in the 2002-2003 timeframe by most leading semiconductor companies The Pentium 4 brand refers to Intel 's line of single- core mainstream desktop and Laptop Central processing units (CPUs introduced "MMIV" redirects here For the Modest Mouse album see " Baron von Bullshit Rides Again " Released with it were the E7525 (workstation), E7520 and E7320 (both server) chipsets, which added support for PCI Express, DDR-II and Serial ATA. Not to be confused with PCI-X, a different bus architecture Peripheral Component Interconnect Express, officially abbreviated as PCI-E The Xeon was noticeably slower than AMD's Opteron, although it could be faster in situations where Hyper-Threading came into play.
A slightly updated core called "Irwindale" was released in early 2005, with twice the L2 cache of Nocona and able to reduce its clockspeeds during low processor demand. However, independent tests showed that AMD's Opteron still outperformed Irwindale.
64-bit Xeon MPs were introduced in April 2005. The cheaper "Cranford" was an MP version of Nocona, while the more expensive "Potomac" was a Cranford with 8 MB of L3 cache. All these Prescott-derived Xeons have the product code 80546.
| Xeon processor family | |
|---|---|
| Original logo | 2008 New logo |
The first dual-core CPU branded Xeon, codenamed Paxville DP, product code 80551, was released by Intel on 10 October 2005. A multi-core processor (or chip-level multiprocessor, CMP) combines two or more independent cores into a single package composed of a single Integrated Events 680 - Battle of Karbala: Shia Imam Husayn bin Ali, the grandson of the Prophet Muhammad, is decapitated Year 2005 ( MMV) was a Common year starting on Saturday (link displays full calendar of the Gregorian calendar. Paxville DP had NetBurst architecture, and was a dual-core equivalent of the single-core Irwindale (related to the Pentium D branded "Smithfield"") with 4 MB of L2 Cache (2 MB per core). The Pentium D brand refers to two series of Dual-core 64-bit X86 processors with the NetBurst Microarchitecture manufactured The Pentium D brand refers to two series of Dual-core 64-bit X86 processors with the NetBurst Microarchitecture manufactured The only one Paxville DP model released ran at 2. 8 GHz, featured an 800 MT/s front side bus, and was produced using a 90 nm process.
An MP-capable version of Paxville DP, codenamed Paxville MP, product code 80560, was released on 1 November 2005. Events 996 - Emperor Otto III issues a deed to Gottschalk Bishop of Freising which is the oldest known document using the name Ostarrîchi Year 2005 ( MMV) was a Common year starting on Saturday (link displays full calendar of the Gregorian calendar. There are two versions: one with 2 MB of L2 Cache (1 MB per core), and one with 4 MB of L2 (2 MB per core). Paxville MP, called the dual-core Xeon 7000-series, was produced using a 90 nm process. Paxville MP clock ranges between 2. 67 and 3. 0 GHz (model numbers 7020-7041), with some models having a 667 MT/s FSB, and others having an 800 MT/s FSB.
| Model | Speed (GHz) | L2 Cache (MB) | FSB (MHz) | TDP (Watts) |
|---|---|---|---|---|
| 7020 | 2. 66 | 2x1 | 667 | 165 |
| 7030 | 2. 80 | 2x1 | 800 | 165 |
| 7040 | 3. 00 | 2x2 | 667 | 165 |
| 7041 | 3. 00 | 2x2 | 800 | 165 |
On 14 March 2006, Intel released a dual-core processor codenamed Sossaman and branded as Xeon LV (low-voltage). Events 1489 - The Queen of Cyprus, Catherine Cornaro, sells her kingdom to Venice. Year 2006 ( MMVI) was a Common year starting on Sunday of the Gregorian calendar. Subsequently a ULV (ultra-low-voltage) version was released. The Sossaman was a low-/ultra-low-power and double-processor capable CPU (like AMD Quad FX), based on the "Yonah" processor, for ultradense non-consumer environment (i.e. targeted at the blade-server and embedded markets), and it was rated at a thermal design power (TDP) of 31 watts (LV: 1. The AMD Quad FX platform is an AMD platform targeted at enthusiasts which allows users to plug two Socket F Athlon 64 FX or 2-way Opteron The Core brand refers to Intel 's 32-bit mobile Dual-core X86 CPUs that derived from the Pentium M branded processors M N O The Thermal Design Power (TDP (sometimes called Thermal Design Point) represents the maximum amount of power the cooling system in a computer is required to dissipate The watt (symbol W) is the SI derived unit of power, equal to one Joule of energy per Second. 66 and 2 GHz ) and 15 W (ULV: 1. The watt (symbol W) is the SI derived unit of power, equal to one Joule of energy per Second. 66 GHz)[1]. As such, it supported most of the same features as earlier Xeons: Virtualization Technology, 667 MT/s front side bus, and dual-core processing, but it did not support 64-bit operations, so it could not run 64-bit-only server software, such as Microsoft Exchange Server 2007, and therefore it was limited to only 16 GB of memory. Microsoft Exchange Server is a Messaging and Collaborative software product developed by Microsoft. A planned successor, codenamed "Merom MP" was to be a drop-in upgrade to allow Sossaman-based servers to upgrade to 64-bit capability. The Core 2 brand refers to a range of Intel 's consumer 64-bit dual-core and 2x2 MCM quad-core CPUs with the X86-64 instruction set However, this was abandoned in favour of low-voltage versions of the Woodcrest LV processor leaving the Sossaman at a dead-end with no planned upgrades. The Xeon brand refers to many families of Intel 's x86 Multiprocessing CPUs – for dual-processor (DP and multi-processor (MP configuration
On 23 May 2006, Intel released the dual-core CPU (Xeon branded 5000 series) codenamed Dempsey (product code 80555). Events 1430 - Siege of Compiègne: Joan of Arc is captured by the Burgundians while leading an army to relieve Compiègne Year 2006 ( MMVI) was a Common year starting on Sunday of the Gregorian calendar. Released as the Dual-Core Xeon 5000-series, Dempsey is a NetBurst architecture processor produced using a 65 nm process, and is virtually identical to Intel's "Presler" Pentium Extreme Edition, except for the addition of SMP support, which lets Dempsey operate in dual-processor systems. The Pentium D brand refers to two series of Dual-core 64-bit X86 processors with the NetBurst Microarchitecture manufactured The Pentium D brand refers to two series of Dual-core 64-bit X86 processors with the NetBurst Microarchitecture manufactured Dempsey ranges between 2. 50 and 3. 73 GHz (model numbers 5020-5080). Some models have a 667 MT/s FSB, and others have a 1066 MT/s FSB. Dempsey has 4 MB of L2 Cache (2 MB per core). A Medium Voltage model, at 3. 2 GHz and 1066 MT/s FSB (model number 5063), has also been released. Dempsey also introduces a new interface for Xeon processors: Socket J, also known as LGA 771. Socket J, also known as LGA 771, is a CPU interface introduced by Intel in 2006 Socket J, also known as LGA 771, is a CPU interface introduced by Intel in 2006
| Model | Speed (GHz) | L2 Cache (MB) | FSB (MHz) | TDP (Watts) |
|---|---|---|---|---|
| 5020 | 2. 50 | 2x2 | 667 | 95 |
| 5030 | 2. 66 | 2x2 | 667 | 95 |
| 5040 | 2. 83 | 2x2 | 667 | 95 |
| 5050 | 3. 00 | 2x2 | 667 | 95 |
| 5060 | 3. 20 | 2x2 | 1066 | 130 |
| 5063 | 3. 20 | 2x2 | 1066 | 95 |
| 5070 | 3. 46 | 2x2 | 1066 | 130 |
| 5080 | 3. 73 | 2x2 | 1066 | 130 |
On 26 June 2006, Intel released the dual-core CPU (Xeon branded 5100 series) codenamed Woodcrest (product code 80556); it was the first Intel Core microarchitecture processor to be launched on the market. Events 363 - Roman Emperor Julian is killed during the retreat from the Sassanid Empire. Year 2006 ( MMVI) was a Common year starting on Sunday of the Gregorian calendar. The Intel Core microarchitecture (previously known as the Intel Next-Generation Micro-Architecture, or NGMA is a multi-core processor It is a server and workstation version of the Intel Core 2 processor. The Core 2 brand refers to a range of Intel 's consumer 64-bit dual-core and 2x2 MCM quad-core CPUs with the X86-64 instruction set Intel claims that it provides an 80% boost in performance, while reducing power consumption by 20% relative to the Pentium D.
Most models have a 1333 MT/s FSB, except for the 5110 and 5120, which have a 1066 MT/s FSB. The fastest processor (5160) operates at 3. 0 GHz. All Woodcrests use LGA 771 and all except two models have a TDP of 65 watts. Socket J, also known as LGA 771, is a CPU interface introduced by Intel in 2006 The 5160 has a TDP of 80 W and the 5148LV (2. 33 GHz), has a TDP of 40 W. The previous generation Xeons had a TDP of 130 W. All models support Intel 64 (Intel's x86-64 implementation), the XD bit, and Virtualization Technology, with the "Demand Based Switching" power management option only on Dual-Core Xeon 5140 or above. The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (or code x86 virtualization is the method by which X86 -based "guest" operating systems are run under another "host" x86 operating system with little or no modification Intel Demand Based Switching (DBS is a re-marketing of Intel's " SpeedStep " technology to the server marketplace Woodcrest has 4 MB of shared L2 Cache.
| Model | Speed (GHz) | L2 Cache (MB) | FSB (MHz) | TDP (Watts) |
|---|---|---|---|---|
| 5110 | 1. 60 | 4 | 1066 | 65 |
| 5120 | 1. 83 | 4 | 1066 | 65 |
| 5128 | 1. 83 | 4 | 1066 | 40 |
| 5138 | 2. 13 | 4 | 1066 | 35 |
| 5140 | 2. 33 | 4 | 1333 | 65 |
| 5148 | 2. 33 | 4 | 1333 | 40 |
| 5150 | 2. 66 | 4 | 1333 | 65 |
| 5160 | 3 | 4 | 1333 | 80 |
On 11 November 2007, Intel released the dual-core CPU (Xeon branded 5200 series) codenamed Wolfdale DP (product code 80573),[2] it is built on a 45 nm process like the desktop Core 2 Duo Wolfdale and the Xeon-SP Wolfdale, featuring Intel 64 (Intel's x86-64 implementation), the XD bit, and Virtualization Technology, it is unclear whether the "Demand Based Switching" power management will be available on the L5238 which is scheduled for April 2008. Events 308 - The Congress of Carnuntum: Attempting to keep peace within the Roman Empire, the leaders of the Tetrarchy declare Year 2007 ( MMVII) was a Common year starting on Monday of the Gregorian calendar in the 21st century. The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (or code x86 virtualization is the method by which X86 -based "guest" operating systems are run under another "host" x86 operating system with little or no modification Intel Demand Based Switching (DBS is a re-marketing of Intel's " SpeedStep " technology to the server marketplace [3] Wolfdale has 6 MB of shared L2 Cache.
| Model | Speed (GHz) | L2 Cache (MB) | FSB (MHz) | TDP (Watts) |
|---|---|---|---|---|
| E5205 | 1. 86 | 6 | 1066 | 65 |
| L5238 | ? | 6 | ? | 40 |
| X5260 | 3. 33 | 6 | 1333 | 80 |
| X5272 | 3. 40 | 6 | 1600 | 80 |
Released on 29 August 2006,[4] the 7100 series, codenamed Tulsa (product code 80550), is an improved version of Paxville MP, built on a 65 nm process, with 2 MiB of L2 cache (1 MiB per core) and up to 16 MiB of L3 cache. Events 708 - Copper coins are minted in Japan for the first time (Traditional Japanese date: August 10, 708) Year 2006 ( MMVI) was a Common year starting on Sunday of the Gregorian calendar. It uses Socket 604 [1]. Socket 604 is a motherboard socket for Intel's Xeon processor Tulsa was released in two lines: the N-line uses a 667 MT/s FSB, and the M-line uses an 800 MT/s FSB. The N-line ranges from 2. 5 to 3. 5 GHz (model numbers 7110N-7150N), and the M-line ranges from 2. 6 to 3. 4 GHz (model numbers 7110M-7140M). L3 cache ranges from 4 MiB to 16 MiB across the models. [5]
| Model | Speed (GHz) | L2 Cache (MB) | FSB (MHz) | TDP (Watts) |
|---|---|---|---|---|
| 7110N | 2. 50 | 4 | 667 | 95 |
| 7110M | 2. 60 | 4 | 800 | 95 |
| 7120N | 3. 00 | 4 | 667 | 95 |
| 7120M | 3. 00 | 4 | 800 | 95 |
| 7130N | 3. 16 | 8 | 667 | 150 |
| 7130M | 3. 20 | 8 | 800 | 150 |
| 7140N | 3. 33 | 16 | 667 | 150 |
| 7140M | 3. 40 | 16 | 800 | 150 |
The 7200 series, codenamed Tigerton (product code 80564) is an MP-capable processor, similar to the 7300 series, but, in contrast, only one core is active on each silicon chip, and the other one is turned off (blocked), resulting as a dual-core capable processor. The Xeon brand refers to many families of Intel 's x86 Multiprocessing CPUs – for dual-processor (DP and multi-processor (MP configuration [2] [3][4] [5]
| Model | Speed (GHz) | L2 Cache (MB) | FSB (MHz) | TDP (Watts) |
|---|---|---|---|---|
| E7210 | 2. 40 | 2x4 | 1066 | 80 |
| E7220 | 2. 93 | 2x4 | 1066 | 80 |
The 3000 series, codenamed Conroe (product code 80557) dual-core Xeon (branded) CPU,[6] released at the end of September 2006, was just rebranded version of the Intel's mainstream Conroe otherwise branded as Core 2 Duo (for consumer desktops). Unlike most Xeon processors, they only support single-CPU operation. They use Socket T (LGA775), operate on a 1066 MHz front-side bus, support Enhanced Intel Speedstep Technology and Intel Virtualization Technology but do not support Hyper-Threading. Intel Processors with a number ending in "5" have a 1333 MT/s FSB. [7]
| Model | Speed (GHz) | L2 Cache (MB) | FSB (MHz) | TDP (Watts) |
|---|---|---|---|---|
| 3040 | 1. 86 | 2 | 1066 | 65 |
| 3050 | 2. 13 | 2 | 1066 | 65 |
| 3055* | 2. 13 | 4 | 1066 | 65 |
| 3060 | 2. 4 | 4 | 1066 | 65 |
| 3065 | 2. 33 | 4 | 1333 | 65 |
| 3070 | 2. 66 | 4 | 1066 | 65 |
| 3075 | 2. 66 | 4 | 1333 | 65 |
| 3080* | 2. 93 | 4 | 1066 | 65 |
| 3085 | 3. 00 | 4 | 1333 | 65 |
The 3100 series, codenamed Wolfdale (product code 80570) dual-core Xeon (branded) CPU, was just rebranded version of the Intel's mainstream Wolfdale featuring the same 45 nm process and 6 MB of L2 cache. Unlike most Xeon processors, they only support single-CPU operation. They use Socket T (LGA775), operate on a 1333 MHz front-side bus, support Enhanced Intel Speedstep Technology and Intel Virtualization Technology but do not support Hyper-Threading. There is currently only one representant in this class named E3110.
| Model | Speed (GHz) | L2 Cache (MB) | FSB (MHz) | TDP (Watts) |
|---|---|---|---|---|
| E3110 | 3. 00 | 6 | 1333 | 65 |
Intel released relabeled versions of its quad-core (2x2) Core 2 Quad processor as the Xeon 3200-series (product code 80562) on 7 January 2007. Events 1325 - Alfonso IV becomes King of Portugal. 1558 - France takes Calais, the last continental Year 2007 ( MMVII) was a Common year starting on Monday of the Gregorian calendar in the 21st century. [9] The 2x2 "quad-core" (dual-die dual-core[10]) comprised two separate dual-core die next to each other in one CPU package. The models are the X3210, X3220 and X3230, running at 2. 13, 2. 4 and 2. 66 GHz, respectively. [11] Like the 3000-series, these models only support single-CPU operation and operate on a 1066 MHz front-side bus. It is targeted at the "blade" market.
| Model | Speed (GHz) | L2 Cache (MB) | FSB (MHz) | TDP (Watts) |
|---|---|---|---|---|
| X3210 | 2. 13 | 2x4 | 1066 | 100/105 |
| X3220 | 2. 40 | 2x4 | 1066 | 100/105 |
| X3230 | 2. 66 | 2x4 | 1066 | 100 |
Intel released relabeled versions of its quad-core (2x2) Core 2 Quad processor as the Xeon 3300-series (product code 80569) comprised two separate dual-core dies next to each other in one CPU package and manufactured in a 45 nm process. The models are the X3320, X3350 and X3360, running at 2. 50, 2. 66 and 2. 8 GHz, respectively. The L2 cache is a unified 6 MB per die (except for the X3320 with a smaller 3 MB L2 cache per die), and a front-side bus of 1333 MHz. All models feature Intel 64 (Intel's x86-64 implementation), the XD bit, and Virtualization Technology, as well as "Demand Based Switching". The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (or code x86 virtualization is the method by which X86 -based "guest" operating systems are run under another "host" x86 operating system with little or no modification Intel Demand Based Switching (DBS is a re-marketing of Intel's " SpeedStep " technology to the server marketplace
| Model | Speed (GHz) | L2 Cache (MB) | FSB (MHz) | TDP (Watts) | Socket Platform |
|---|---|---|---|---|---|
| X3320* | 2. 50 | 2x3 | 1333 | 95 | LGA socket 775 |
| X3350 | 2. 66 | 2x6 | 1333 | 95 | LGA socket 775 |
| X3360 | 2. 83 | 2x6 | 1333 | 95 | LGA socket 775 |
A quad-core (2x2) successor of the Woodcrest for DP segment, consisting of two dual-core Woodcrest chips in one package similarly to the dual-core Pentium D branded CPUs (two single-core chips) or the quad-core Kentsfield. The Core 2 brand refers to a range of Intel 's consumer 64-bit dual-core and 2x2 MCM quad-core CPUs with the X86-64 instruction set The Clovertown has been usually implemented with two Woodcrest dies on a multi-chip module, with 8 MB of L2 cache (4 MB per die). A Multi-Chip Module (MCM is a specialized electronic package where multiple Integrated circuits (ICs semiconductor dies or other modules are packaged in such a way as Like Woodcrest, lower models use a 1066 MT/s FSB, and higher models use a 1333 MT/s FSB. Intel released Clovertown, product code 80563, on 14 November 2006[12] with models E5310, E5320, E5335, E5345, and X5355, ranging from 1. Events 1533 - Conquistadors from Spain under the leadership of Francisco Pizarro arrive in Cajamarca, Inca Year 2006 ( MMVI) was a Common year starting on Sunday of the Gregorian calendar. 6 to 2. 66 GHz. The E and X designations are borrowed from Intel's Core 2 model numbering scheme; an ending of -0 implies a 1066 MT/s FSB, and an ending of -5 implies a 1333 MT/s FSB. [11] All models have a TDP of 80 W with the exception of the X5355, which has a TDP of 120 W. A low-voltage version of Clovertown with a TDP of 50 W has a model numbers L5310, L5320 and L5335 (1. 6, 1. 86 and 2. 0 GHz respectively). The 3. 0 GHz X5365 arrived in July 2007, and became available in the Apple Mac Pro [6] on 4 April 2007. Apple Inc, ( formerly Apple Computer Inc, is an American Multinational corporation with a focus on designing and manufacturing Consumer electronics The Mac Pro is a Workstation computer manufactured by Apple Inc Events 1581 - Francis Drake completes a circumnavigation of the world and is knighted by Elizabeth I. Year 2007 ( MMVII) was a Common year starting on Monday of the Gregorian calendar in the 21st century. [7][13] The X5365 is among the fastest processors, performing up to around 38 GFLOPS in the LINPACK benchmark. [8]
| Model | Speed (GHz) | L2 Cache (MB) | FSB (MHz) | TDP (Watts) |
|---|---|---|---|---|
| E5310 | 1. 60 | 2x4 | 1066 | 80 |
| L5310 | 1. 60 | 2x4 | 1066 | 50 |
| E5320 | 1. 83 | 2x4 | 1066 | 80 |
| L5320 | 1. 83 | 2x4 | 1066 | 50 |
| E5335 | 2. 00 | 2x4 | 1333 | 80 |
| L5335 | 2. 00 | 2x4 | 1333 | 50 |
| E5345 | 2. 33 | 2x4 | 1333 | 80 |
| X5355 | 2. 66 | 2x4 | 1333 | 120 |
| X5365 | 3. 00 | 2x4 | 1333 | 120 |
On 11 November 2007 Intel presented Yorkfield based Xeons - called Harpertown (product code 80574) - to the public. Events 308 - The Congress of Carnuntum: Attempting to keep peace within the Roman Empire, the leaders of the Tetrarchy declare Year 2007 ( MMVII) was a Common year starting on Monday of the Gregorian calendar in the 21st century. The Core 2 brand refers to a range of Intel 's consumer 64-bit dual-core and 2x2 MCM quad-core CPUs with the X86-64 instruction set [9] This family comes with a dual die quad-core manufactured on a 45 nm process and featuring 1333 to 1600 MHz front-side bus, the TDP is rated from 50 to 150 Watts depending on the model. All models feature Intel 64 (Intel's x86-64 implementation), the XD bit, and Virtualization Technology, as well as the "Demand Based Switching", except the E5405, which lacks this feature. The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (or code x86 virtualization is the method by which X86 -based "guest" operating systems are run under another "host" x86 operating system with little or no modification Intel Demand Based Switching (DBS is a re-marketing of Intel's " SpeedStep " technology to the server marketplace The supplementary character in front of the model-number represents the thermal rating: an L depicts an TDP of 50 Watts, an E depicts 80 Watts whereas a X is 120 Watts TDP or above. The speed of 3. 00 GHz comes as four models, two models with 80 Watts TDP two other models with 120 Watts TDP with 1333 or 1600 MHz front-side bus respectively. The fastest Harpertown is the X5482 whose TDP of 150 Watts is higher than those of the Prescott-based Xeon DP but having twice as many cores. (This CPU is also sold under the name "Core 2 Extreme QX9775" for use in the Intel SkullTrail system. Intel's Skulltrail is an enthusiast gaming platform that was released on February 19, 2008. )
Intel 1600 MHz front-side bus Xeon processors will drop into the Seaburg chipset whereas several mainboards featuring the Intel 5000/5200-chipset are abled to run the processors with 1333 MHz front-side bus processors. Seaburg features support for dual PCIe 2. 0 x16 slots and up to 128 GB of memory. [14][15]
| Model | Speed (GHz) | L2 Cache (MB) | FSB (MHz) | TDP (Watts) |
|---|---|---|---|---|
| E5405 | 2. 00 | 2x6 | 1333 | 80 |
| E5410 | 2. 33 | 2x6 | 1333 | 80 |
| L5410 | 2. 33 | 2x6 | 1333 | 50 |
| E5420 | 2. 50 | 2x6 | 1333 | 80 |
| L5420 | 2. 50 | 2x6 | 1333 | 50 |
| E5430 | 2. 66 | 2x6 | 1333 | 80 |
| E5440 | 2. 83 | 2x6 | 1333 | 80 |
| E5450 | 3. 00 | 2x6 | 1333 | 80 |
| X5450 | 3. 00 | 2x6 | 1333 | 120 |
| X5460 | 3. 16 | 2x6 | 1333 | 120 |
| E5462 | 2. 80 | 2x6 | 1600 | 80 |
| E5472 | 3. 00 | 2x6 | 1600 | 80 |
| X5472 | 3. 00 | 2x6 | 1600 | 120 |
| X5482 | 3. 20 | 2x6 | 1600 | 150 |
The 7300 series, codenamed Tigerton (product code 80565) is a four-socket (packaged in Socket 604) and greater capable quad-core processor, consisting of two dual core Core2 architecture silicon chips on a single ceramic module, similar to Intel's Xeon 5300 series Clovertown processor modules. Socket 604 is a motherboard socket for Intel's Xeon processor It was announced on 5 September 2007 [10], and is currently shipping. Events 1590 - Alexander Farnese 's army forces Henry IV of France to raise the siege of Paris. Year 2007 ( MMVII) was a Common year starting on Monday of the Gregorian calendar in the 21st century.
The 7300 series uses Intel's Caneland (Clarksboro) platform.
Intel claims the 7300 series Xeons offer more than twice the performance and more than three times the performance per watt as Intel's previous generation 7100 series. The 7300 series' Caneland chipset provides a point to point interface allowing the full front side bus bandwidth per processor.
The 7xxx series is aimed at the large server market, supporting configurations of up to 32 CPUs per host.
| model | Speed (GHz) | L2 Cache (MB) | FSB (MHz) | TDP (Watts) |
|---|---|---|---|---|
| E7310 | 1. 60 | 2x2 | 1066 | 80 |
| E7320 | 2. 13 | 2x2 | 1066 | 80 |
| E7330 | 2. 40 | 2x3 | 1066 | 80 |
| E7340 | 2. 40 | 2x4 | 1066 | 80 |
| L7345 | 1. 86 | 2x4 | 1066 | 50 |
| X7350 | 2. 93 | 2x4 | 1066 | 130 |
A quad-core processor, partially based on Woodcrest, and would have used the new QuickPath Interconnect bus, a bus shared with the Itanium 2 processors of its generation (beginning with the "Tukwila" core). The Intel QuickPath Interconnect or simply " QuickPath " (the official legal name for Common System Interface or " CSI " is a point-to-point Whitefield would have had 16 MB of L2 cache, manufactured using the 65 nm process initially, and the 45 nm process later. The 65 nanometer (65 nm process is an advanced lithographic node used in volume CMOS Semiconductor fabrication. Per the International Technology Roadmap for Semiconductors the 45 nm technology node should refer to the average half-pitch of a memory cell manufactured at around the 2007-2008 time
Whitefield was the first full processor being worked on at Whitefield, Bangalore, India. Whitefield is a suburb of Bangalore in the state of Karnataka, India. Bangalore ( officially Bengaluru ( Kannada: ಬೆಂಗಳೂರು) is the capital of the Indian state of Karnataka. India, officially the Republic of India (भारत गणराज्य inc-Latn Bhārat Gaṇarājya; see also other Indian languages) is a country It was cancelled from the processor roadmap and replaced with Tigerton. [16][17]
Aliceton was a successor to Tigerton. [18] It has effectively been renamed Dunnington as the original Dunnington was based on the now cancelled Whitefield.
Dunnington - the last CPU of the Penryn generation and the Intel's first multi-core (above two) die - will feature a single-die six core design with three unified 3 MiB L2 caches (resembling three merged 45 nm dual-core Wolfdale dies), and 96 KiB L1 cache (Data) and 16 MiB of L3 cache. A multi-core processor (or chip-level multiprocessor, CMP) combines two or more independent cores into a single package composed of a single Integrated It is expected to feature 1066 MHz FSB, fit into the Tigerton's mPGA604 socket, and be compatible with the Caneland chipset. These processors are expected to support DDR2-1066 (266 MHz), and to have a max. power consumption (TDP) below 130 watts. The Thermal Design Power (TDP (sometimes called Thermal Design Point) represents the maximum amount of power the cooling system in a computer is required to dissipate They are intended for blades and other stacked computer systems. Availability is scheduled for the second half of 2008. It will be followed shortly by the Nehalem microarchitecture.
| model | Speed (GHz) | L3 Cache (MB) | FSB (MHz) | TDP (Watts) | Cores |
|---|---|---|---|---|---|
| X7470 | 2. 66 | 16 | 1066 | 130 | 6 |
| E7459 | 2. 40 | 12 | 1066 | 95 | 6 |
| E7440 | 2. 40 | 12 | 1066 | 95 | 4 |
| E7430 | 2. 13 | 12 | 1066 | 65 | 4 |
| E7420 | 2. 13 | 8 | 1066 | 65 | 4 |
| L7455 | 2. 13 | 12 | 1066 | 65 | 6 |
| L7445 | 2. 13 | 12 | 1066 | 65 | 4 |
Gainestown is a quad-core processor based on Intel's upcoming Nehalem microarchitecture. [11]
This Nehalem-based, MP-capable processor with eight or more cores is expected to be launched within 2008. [20]
Supercomputers based on Xeon processors in the top ten of the Top500 fastest supercomputers in the world: