A superscalar CPU architecture implements a form of parallelism called Instruction-level parallelism within a single processor. The Cray T3E was Cray Research 's second-generation Massively parallel supercomputer architecture launched in 1995 Alpha, originally known as Alpha AXP, was a 64-bit Reduced instruction set computer (RISC Instruction set architecture (ISA developed Parallel computing is a form of computation in which many instructions are carried out simultaneously operating on the principle that large problems can often Instruction-level parallelism (ILP is a measure of how many of the operations in a Computer program can be performed simultaneously It thereby allows faster CPU throughput than would otherwise be possible at the same clock rate. In Communication networks, such as Ethernet or Packet radio, throughput is the average rate of successful message delivery over a communication channel The clock rate is the fundamental rate in cycles per second (measured in Hertz) at which a Computer performs its most basic operations such as adding two A superscalar processor executes more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to redundant functional units on the processor. Each functional unit is not a separate CPU core but an execution resource within a single CPU such as an arithmetic logic unit, a bit shifter, or a multiplier. In Computing, an arithmetic logic unit ( ALU) is a Digital circuit that performs Arithmetic and Logical operations In digital design, a multiplier or multiplication ALU is a hardware circuit dedicated to multiplying two binary values
While a superscalar CPU is typically also pipelined, they are two different performance enhancement techniques. In Computing, a pipeline is a set of data processing elements connected in series so that the output of one element is the input of the next one It is theoretically possible to have a non-pipelined superscalar CPU or a pipelined non-superscalar CPU.
The superscalar technique is traditionally associated with several identifying characteristics. Note these are applied within a given CPU core.
- Instructions are issued from a sequential instruction stream
- CPU hardware dynamically checks for data dependencies between instructions at run time (versus software checking at compile time)
- Accepts multiple instructions per clock cycle
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History
Seymour Cray's CDC 6600 from 1965 is often mentioned as the first superscalar design. A data dependency in computer science is a situation in which a program statement (instruction refers to the data of a preceding statement In Computer science, compile time refers to either the operations performed by a Compiler (the "compile-time operations" or Programming language Seymour Roger Cray ( September 28, 1925 – October 5, 1996) was a U The CDC 6600 was a Mainframe computer from Control Data Corporation, first delivered in 1964. Year 1965 ( MCMLXV) was a Common year starting on Friday (link will display full calendar of the 1965 Gregorian calendar. The Intel i960CA (1988) and the AMD 29000-series 29050 (1990) microprocessors were the first commercial single chip superscalar microprocessors. Intel 's i960 (or 80960) was a RISC -based Microprocessor design that became popular during the early 1990s as an embedded AMD 29000, often simply 29k, was a popular family of RISC -based 32-bit Microprocessors and Microcontrollers from Advanced Micro Devices RISC CPUs like these brought the superscalar concept to micro computers because the RISC design results in a simple core, allowing straightforward instruction dispatch and the inclusion of multiple functional units (such as ALUs) on a single CPU in the constrained design rules of the time. This was the reason that RISC designs were faster than CISC designs through the 1980s and into the 1990s.
Except for CPUs used in some battery-powered devices, essentially all general-purpose CPUs developed since about 1998 are superscalar. In electronics a battery is a combination of two or more Electrochemical cells which store chemical Energy which can be converted into electrical energy Beginning with the "P6" (Pentium Pro and Pentium II) implementation, Intel's x86 architecture microprocessors have implemented a CISC instruction set on a superscalar RISC microarchitecture. The P6 Microarchitecture is the sixth generation Intel X86 Microprocessor architecture released in 1995. The Pentium Pro is a sixth-generation X86 -based Microprocessor developed and manufactured by Intel introduced in November 1995 The Pentium II brand refers to Intel 's sixth-generation Microarchitecture (" Intel P6 " and x86 -compatible Microprocessors See also X86 assembly language The generic term x86 refers to the most commercially successful Instruction set architecture in the history of Personal In Computer engineering, microarchitecture (sometime abbreviated to µarch or uarch is a description of the Electrical circuitry of a Computer, Central Complex instructions are internally translated to a RISC-like "micro-ops" RISC instruction set, allowing the processor to take advantage of the higher-performance underlying processor while remaining compatible with earlier Intel processors.
From scalar to superscalar
The simplest processors are scalar processors. Scalar processors represent the simplest class of Computer processors A scalar processor processes one data item at a time (typical data items being integers or Each instruction executed by a scalar processor typically manipulates one or two data items at a time. By contrast, each instruction executed by a vector processor operates simultaneously on many data items. A vector processor, or array processor, is a CPU design where the instruction set includes operations that can perform mathematical operations on multiple data An analogy is the difference between scalar and vector arithmetic. In Linear algebra, Real numbers are called Scalars and relate to vectors in a Vector space through the operation of Scalar multiplication A superscalar processor is sort of a mixture of the two. Each instruction processes one data item, but there are multiple redundant functional units within each CPU thus multiple instructions can be processing separate data items concurrently.
Superscalar CPU design emphasizes improving the instruction dispatcher accuracy, and allowing it to keep the multiple functional units in use at all times. This has become increasingly important when the number of units increased. While early superscalar CPUs would have two ALUs and a single FPU, a modern design like the PowerPC 970 includes four ALUs and two FPUs and a couple of SIMD units too. In Computing, an arithmetic logic unit ( ALU) is a Digital circuit that performs Arithmetic and Logical operations A floating point unit (FPU is a part of a Computer system specially designed to carry out operations on Floating point numbers The PowerPC 970, PowerPC 970FX, PowerPC 970GX, and PowerPC 970MP, are 64-bit Power Architecture processors from IBM In Computing, SIMD ( S ingle I nstruction M ultiple D ata is a technique employed to achieve data level parallelism as in a Vector If the dispatcher is ineffective at keeping all of these units fed with instructions, the performance of the system will suffer.
A superscalar processor usually sustains an execution rate in excess of one instruction per machine cycle. In Computer architecture, Cycles per instruction ( clock cycles per instruction or clocks per instruction or CPI) is a term used to describe one But merely processing multiple instructions concurrently does not make an architecture superscalar, since pipelined, multiprocessor or multi-core architectures also achieve that, but with different methods. Pipelining redirects here For HTTP pipelining see HTTP pipelining. Multiprocessing is the use of two or more central processing units (CPUs within a single computer system A multi-core processor (or chip-level multiprocessor, CMP) combines two or more independent cores into a single package composed of a single Integrated
In a superscalar CPU the dispatcher reads instructions from memory and decides which ones can be run in parallel, dispatching them to redundant functional units contained inside a single CPU. Therefore a superscalar processor can be envisioned having multiple parallel pipelines, each of which is processing instructions simultaneously from a single instruction thread.
Limitations
Available performance improvement from superscalar techniques is limited by two key areas:
- The degree of intrinsic parallelism in the instruction stream, i. e. limited amount of instruction-level parallelism, and
- The complexity and time cost of the dispatcher and associated dependency checking logic.
Existing binary executable programs have varying degrees of intrinsic parallelism. In some cases instructions are not dependent on each other and can be executed simultaneously. In other cases they are inter-dependent: one instruction impacts either resources or results of the other. The instructions a = b + c; d = e + f can be run in parallel because none of the results depend on other calculations. However, the instructions a = b + c; d = a + f might not be runnable in parallel, depending on the order in which the instructions complete while they move through the units.
When the number of simultaneously issued instructions increases, the cost of dependency checking increases extremely rapidly. This is exacerbated by the need to check dependencies at run time and at the CPU's clock rate. This cost includes additional logic gates required to implement the checks, and time delays through those gates. Research shows the gate cost in some cases may be nk gates, and the delay cost k2logn, where n is the number of instructions in the processor's instruction set, and k is the number of simultaneously dispatched instructions. In mathematics, this is called a combinatoric problem involving permutations. Combinatorics is a branch of Pure mathematics concerning the study of discrete (and usually finite) objects In several fields of Mathematics the term permutation is used with different but closely related meanings
Even though the instruction stream may contain no inter-instruction dependencies, a superscalar CPU must nonetheless check for that possibility, since there is no assurance otherwise and failure to detect a dependency would produce incorrect results.
No matter how advanced the semiconductor process or how fast the switching speed, this places a practical limit on how many instructions can be simultaneously dispatched. While process advances will allow ever greater numbers of functional units (e. g, ALUs), the burden of checking instruction dependencies grows so rapidly that the achievable superscalar dispatch limit is fairly small. -- likely on the order of five to six simultaneously dispatched instructions.
However even given infinitely fast dependency checking logic on an otherwise conventional superscalar CPU, if the instruction stream itself has many dependencies, this would also limit the possible speedup. Thus the degree of intrinsic parallelism in the code stream forms a second limitation.
Alternatives
Collectively, these two limits drive investigation into alternative architectural performance increases such as Very Long Instruction Word (VLIW), Explicitly Parallel Instruction Computing (EPIC), simultaneous multithreading (SMT), and multi-core processors. Very Long Instruction Word or VLIW refers to a CPU architecture designed to take advantage of Instruction level parallelism (ILP Explicitly Parallel Instruction Computing ( EPIC) is a term coined in 1997 by the HP-Intel alliance to describe a Computing paradigm that began to be researched Simultaneous multithreading, often abbreviated as SMT, is a technique for improving the overall efficiency of Superscalar CPUs with Hardware A multi-core processor (or chip-level multiprocessor, CMP) combines two or more independent cores into a single package composed of a single Integrated
With VLIW, the burdensome task of dependency checking by hardware logic at run time is removed and delegated to the compiler. A compiler is a Computer program (or set of programs that translates text written in a computer language (the source language) into another Explicitly Parallel Instruction Computing (EPIC) is like VLIW, with extra cache prefetching instructions. Explicitly Parallel Instruction Computing ( EPIC) is a term coined in 1997 by the HP-Intel alliance to describe a Computing paradigm that began to be researched
Simultaneous multithreading, often abbreviated as SMT, is a technique for improving the overall efficiency of superscalar CPUs. Simultaneous multithreading, often abbreviated as SMT, is a technique for improving the overall efficiency of Superscalar CPUs with Hardware SMT permits multiple independent threads of execution to better utilize the resources provided by modern processor architectures.
Superscalar processors differ from multi-core processors in that the redundant functional units are not entire processors. A multi-core processor (or chip-level multiprocessor, CMP) combines two or more independent cores into a single package composed of a single Integrated A single processor is composed of finer-grained functional units such as the ALU, integer multiplier, integer shifter, floating point unit, etc. In Computing, an arithmetic logic unit ( ALU) is a Digital circuit that performs Arithmetic and Logical operations In computer science the term integer is used to refer to a Data type which represents some finite subset of the mathematical Integers These are also known as In digital design, a multiplier or multiplication ALU is a hardware circuit dedicated to multiplying two binary values A floating point unit (FPU is a part of a Computer system specially designed to carry out operations on Floating point numbers There may be multiple versions of each functional unit to enable execution of many instructions in parallel. This differs from a multicore CPU that concurrently processes instructions from multiple threads, one thread per core. A multi-core processor (or chip-level multiprocessor, CMP) combines two or more independent cores into a single package composed of a single Integrated It also differs from a pipelined CPU, where the multiple instructions can concurrently be in various stages of execution, assembly-line fashion. Pipelining redirects here For HTTP pipelining see HTTP pipelining. An assembly line is a Manufacturing process in which parts (usually Interchangeable parts) are added to a product in a sequential manner using optimally planned
The various alternative techniques are not mutually exclusive—they can be (and frequently are) combined in a single processor. Thus a multicore CPU is possible where each core is an independent processor containing multiple parallel pipelines, each pipeline being superscalar. Some processors also include vector capability. A vector processor, or array processor, is a CPU design where the instruction set includes operations that can perform mathematical operations on multiple data
See also
- Super-threading
- Simultaneous multithreading
- Speculative execution / Eager execution
- Software lockout, a multiprocessor issue similar to logic dependencies on superscalars
References
- Mike Johnson, Superscalar Microprocessor Design, Prentice-Hall, 1991, ISBN 0-13-875634-1
- Sorin Cotofana, Stamatis Vassiliadis, "On the Design Complexity of the Issue Logic of Superscalar Machines", EUROMICRO 1998: 10277-10284
- Steven McGeady, "The 1960CA SuperScalar Implementation of the 80960 Architecture", IEEE 1990, pp. Super-threading is a multithreading approach that weaves together the execution of different threads on a single processor without truly executing them at the same time Simultaneous multithreading, often abbreviated as SMT, is a technique for improving the overall efficiency of Superscalar CPUs with Hardware In Computer science, speculative execution is the execution of code, the result of which may not be needed Eager evaluation or strict evaluation is the Evaluation strategy in most traditional Programming languages In eager evaluation an expression In Multiprocessor computer systems software lockout is the issue of performance degradation due to the idle wait times spent by the CPUs in kernel -level Dr William Michael "Mike" Johnson is a technologist and pioneer in Superscalar Microprocessor design EUROMICRO is an international scientific engineering and educational organization dedicated to advancing the arts sciences and applications of Information technology and Steven McGeady is a former Intel executive best known as a witness in the Microsoft Antitrust Trial. 232-240
- Steven McGeady, et al. Steven McGeady is a former Intel executive best known as a witness in the Microsoft Antitrust Trial. , "Performance Enhancements in the Superscalar i960MM Embedded Microprocessor," ACM Proceedings of the 1991 Conference on Computer Architecture (Compcon), 1991, pp. 4-7
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