Sempron
Central processing unit |

AMD Sempron Logo |
| Produced: |
July 2004 - Current |
| Manufacturer: |
AMD |
| Max CPU clock: |
1. 4 GHz to 2. The hertz (symbol Hz) is a measure of Frequency, informally defined as the number of events occurring per Second. 2 GHz |
| FSB speeds: |
166 MHz to 200 MHz |
| Instruction set: |
x86, AMD64 |
| Sockets:
|
Core names:
- Thoroughbred B/Thorton
- Barton
- Paris
- Palermo (Socket 754, 939)
- Manila (Socket AM2)
- Keene (Socket S1)
|
Socket-A Sempron 3000+
Sempron has been the marketing name used by AMD for several different entry level desktop CPUs, using several different technologies and CPU socket formats. The hertz (symbol Hz) is a measure of Frequency, informally defined as the number of events occurring per Second. In Personal computers the Front Side Bus ( FSB) is the bus that carries data between the CPU and the northbridge. The hertz (symbol Hz) is a measure of Frequency, informally defined as the number of events occurring per Second. The hertz (symbol Hz) is a measure of Frequency, informally defined as the number of events occurring per Second. An instruction set is a list of all the instructions and all their variations that a processor can execute See also X86 assembly language The generic term x86 refers to the most commercially successful Instruction set architecture in the history of Personal x86-64 is a Superset of the x86 instruction set architecture. Socket A (also known as Socket 462) is the CPU socket used for AMD processors ranging from the Athlon Thunderbird to the Socket 754 is a CPU socket originally developed by AMD to succeed its Athlon XP platform (Socket 462 also referred to as Socket A) Socket 939 is a CPU socket released by AMD in June 2004 to supersede the previous Socket 754 for Athlon 64 processors The Socket AM2, renamed from Socket M2 (to prevent using the same name as Cyrix MII processors is a CPU socket designed by AMD for desktop Socket S1 is the CPU socket type used by AMD for their Turion 64, Athlon 64 Mobile and later Sempron processors which debuted A CPU socket or CPU slot is a connector on a computer's Motherboard that accepts a CPU and forms an electrical interface with it
The Sempron replaced the AMD Duron processor and competes against Intel's Celeron D processor. The AMD Duron was an X86 -compatible Computer processor manufactured by AMD. The Celeron brand is a range of X86 CPUs from Intel targeted at budget/value Personal computers €”with the motto "delivering great quality
AMD coined the name from the Latin semper, which means "always, everyday", to denote that the Sempron was the right processor for everyday computing [1].
History and features
The first Sempron CPUs were based on the Athlon XP architecture using the Thoroughbred or Thorton core. Athlon is the brand name applied to a series of different X86 processors designed and manufactured by AMD. These models were equipped with the Socket A interface, 256 KiB L2 cache and 166 MHz Front side bus (FSB 333). Socket A (also known as Socket 462) is the CPU socket used for AMD processors ranging from the Athlon Thunderbird to the A kibibyte (a contraction of ki lo bi nary byte) is a unit of Information or Computer storage, established by the International In Personal computers the Front Side Bus ( FSB) is the bus that carries data between the CPU and the northbridge. Thoroughbred cores natively had 256 KiB L2 cache, but Thortons had 512 KiB L2 cache, half of which was disabled and could sometimes be reactivated by bridge modification. Later, AMD introduced the Sempron 3000+ CPU, based on the Barton core with 512 KiB L2 cache. From a hardware and user standpoint, the Socket A Sempron CPUs were essentially identical to Athlon XP desktop CPUs with a new brand name. AMD has ceased production of all Socket A Sempron CPUs.
The second generation (Paris/Palermo core) was based on the architecture of the Socket 754 Athlon 64. Socket 754 is a CPU socket originally developed by AMD to succeed its Athlon XP platform (Socket 462 also referred to as Socket A) The Athlon 64 is an eighth-generation AMD64 architecture Microprocessor produced by AMD, released on Some differences from Athlon 64 processors include a reduced cache size (either 128 or 256 KiB L2), and the absence of AMD64 support in earlier models. Apart from these differences, the Socket 754 Sempron CPUs share most features with the more powerful Athlon 64, including an integrated (on-die) memory controller, the HyperTransport link, and AMD's "NX bit" feature. The memory controller is a chip on a computer's Motherboard or CPU die which manages the flow of data going to and from the memory. The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (or code
In the second half of 2005, AMD added 64-bit support (AMD64) to the Sempron line. x86-64 is a Superset of the x86 instruction set architecture. Some journalists (but not AMD) often refer to this revision of chips as "Sempron 64" to distinguish it from the previous revision. AMD's intent in releasing 64-bit entry-level processors was to extend the market for 64-bit processors, which at the time of Sempron 64's first release, was a niche market. A niche market is a focused targetable portion (subset of a market
In 2006, AMD announced the Socket AM2 and Socket S1 line of Sempron processors. The Socket AM2, renamed from Socket M2 (to prevent using the same name as Cyrix MII processors is a CPU socket designed by AMD for desktop Socket S1 is the CPU socket type used by AMD for their Turion 64, Athlon 64 Mobile and later Sempron processors which debuted These are functionally equivalent to the previous generation, except they have a dual-channel DDR2 SDRAM memory controller which replaces the single-channel DDR SDRAM version. DDR SDRAM ( double data rate synchronous dynamic random access memory) is a class of memory Integrated circuit used in Computers It achieves nearly twice The TDP of the standard version remains at 62 W (watts), while the new "Energy Efficient Small Form Factor" version has a reduced 35 W TDP. The Thermal Design Power (TDP (sometimes called Thermal Design Point) represents the maximum amount of power the cooling system in a computer is required to dissipate The Socket AM2 version also does not require a minimum voltage of 1. 1 volts to operate, whereas all socket 754 Semprons with Cool'n'Quiet did. In 2006, AMD was selling both Socket 754 and Socket AM2 Sempron CPUs concurrently. In the middle of 2007 AMD appears to have dropped the 754 line and is shipping AM2 and S1 Semprons.
Models for Socket A (Socket 462)
Thoroughbred B/Thorton (130 nm)
- L1-Cache: 64 + 64 KiB (Data + Instructions)
- L2-Cache: 256 KiB, fullspeed
- MMX, 3DNow!, SSE
- Socket A (EV6)
- Front side bus: 166 MHz (FSB 333)
- VCore: 1. MMX is a single instruction multiple data (SIMD Instruction set designed by Intel, introduced in 1997 in their Pentium line of 3DNow! is the Trade name of a multimedia extension created by AMD for its processors starting with the K6-2 in 1998 S treaming '''S'''IMD E xtensions ( SSE) is a SIMD (Single Instruction Multiple Data Instruction set extension to the X86 Socket A (also known as Socket 462) is the CPU socket used for AMD processors ranging from the Athlon Thunderbird to the In Personal computers the Front Side Bus ( FSB) is the bus that carries data between the CPU and the northbridge. 6 V
- First release: July 28, 2004
- Clockrate: 1500 MHz - 2000 MHz (2200+ to 2800+)
Barton (130 nm)
- L1-Cache: 64 + 64 KiB (Data + Instructions)
- L2-Cache: 512 KiB, fullspeed
- MMX, 3DNow!, SSE
- Socket A (EV6)
- Front side bus: 166 MHz - 200 MHz (FSB 333 - 400)
- VCore: 1. Events 1540 - Thomas Cromwell is executed at the order of Henry VIII of England on charges of Treason. "MMIV" redirects here For the Modest Mouse album see " Baron von Bullshit Rides Again " MMX is a single instruction multiple data (SIMD Instruction set designed by Intel, introduced in 1997 in their Pentium line of 3DNow! is the Trade name of a multimedia extension created by AMD for its processors starting with the K6-2 in 1998 S treaming '''S'''IMD E xtensions ( SSE) is a SIMD (Single Instruction Multiple Data Instruction set extension to the X86 Socket A (also known as Socket 462) is the CPU socket used for AMD processors ranging from the Athlon Thunderbird to the In Personal computers the Front Side Bus ( FSB) is the bus that carries data between the CPU and the northbridge. 6 - 1. 65 V
- First release: September 17, 2004
- Clockrate: 2000–2200 MHz (Sempron 3000+, Sempron 3300+)
Models for Socket 754
Paris (130 nm SOI)
- L1-Cache: 64 + 64 KiB (Data + Instructions)
- L2-Cache: 256 KiB, fullspeed
- MMX, 3DNow!, SSE, SSE2
- Enhanced Virus Protection (NX bit)
- Integrated 72-bit(Single channel, ECC capable) DDR memory controller
- Socket 754, 800 MHz HyperTransport
- VCore: 1. Events 1176 - The Battle of Myriokephalon is fought 1462 - The Battle of Świecino (or Battle of Żarnowiec "MMIV" redirects here For the Modest Mouse album see " Baron von Bullshit Rides Again " MMX is a single instruction multiple data (SIMD Instruction set designed by Intel, introduced in 1997 in their Pentium line of 3DNow! is the Trade name of a multimedia extension created by AMD for its processors starting with the K6-2 in 1998 S treaming '''S'''IMD E xtensions ( SSE) is a SIMD (Single Instruction Multiple Data Instruction set extension to the X86 SSE2, Streaming SIMD Extensions 2, is one of the IA-32 SIMD (Single Instruction Multiple Data Instruction sets SSE2 was first introduced by The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (or code Socket 754 is a CPU socket originally developed by AMD to succeed its Athlon XP platform (Socket 462 also referred to as Socket A) 4 V
- First release: July 28, 2004
- Clockrate: 1800 MHz (3100+)
- Stepping: CG (Part No. Events 1540 - Thomas Cromwell is executed at the order of Henry VIII of England on charges of Treason. "MMIV" redirects here For the Modest Mouse album see " Baron von Bullshit Rides Again " : *AX)
Palermo (90 nm SOI)
- Early models (stepping D0) are downlabeled "Oakville" mobile Athlon64
- L1-Cache: 64 + 64 KiB (Data + Instructions)
- L2-Cache: 128/256 KiB, fullspeed
- MMX, 3DNow!, SSE, SSE2
- SSE3 support on E3 and E6 steppings
- AMD64 on E6 stepping
- Cool'n'Quiet (Sempron 3000+ and higher)
- Enhanced Virus Protection (NX bit)
- Integrated 72-bit(Single channel, ECC capable) DDR memory controller
- Socket 754, 800 MHz HyperTransport
- VCore: 1. MMX is a single instruction multiple data (SIMD Instruction set designed by Intel, introduced in 1997 in their Pentium line of 3DNow! is the Trade name of a multimedia extension created by AMD for its processors starting with the K6-2 in 1998 S treaming '''S'''IMD E xtensions ( SSE) is a SIMD (Single Instruction Multiple Data Instruction set extension to the X86 SSE2, Streaming SIMD Extensions 2, is one of the IA-32 SIMD (Single Instruction Multiple Data Instruction sets SSE2 was first introduced by SSE3, also known by its Intel code name Prescott New Instructions (PNI, is the third iteration of the SSE instruction set for the IA-32 architecture x86-64 is a Superset of the x86 instruction set architecture. Cool'n'Quiet is a CPU speed throttling and power saving technology introduced by AMD with their Athlon 64 processor line The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (or code Socket 754 is a CPU socket originally developed by AMD to succeed its Athlon XP platform (Socket 462 also referred to as Socket A) 4 V
- First release: February 2005
- Clockrate: 1400–2000 MHz
- 128 KiB L2-Cache (Sempron 2600+, 3000+, 3300+)
- 256 KiB L2-Cache (Sempron 2500+, 2800+, 3100+, 3400+)
- Steppings: D0 (Part No. : *BA), E3 (Part No. : *BO), E6 (Part No. : *BX)
Models for Socket 939
Palermo (90 nm SOI)
- L1-Cache: 64 + 64 KiB (Data + Instructions)
- L2-Cache: 128/256 KiB, fullspeed
- MMX, 3DNow!, SSE, SSE2, SSE3, AMD64 (E6 Steppings Only), Cool'n'Quiet, NX bit
- Integrated 144-bit(Dual channel, ECC capable) DDR memory controller
- Socket 939, 800 MHz HyperTransport
- VCore: 1. MMX is a single instruction multiple data (SIMD Instruction set designed by Intel, introduced in 1997 in their Pentium line of 3DNow! is the Trade name of a multimedia extension created by AMD for its processors starting with the K6-2 in 1998 S treaming '''S'''IMD E xtensions ( SSE) is a SIMD (Single Instruction Multiple Data Instruction set extension to the X86 SSE2, Streaming SIMD Extensions 2, is one of the IA-32 SIMD (Single Instruction Multiple Data Instruction sets SSE2 was first introduced by SSE3, also known by its Intel code name Prescott New Instructions (PNI, is the third iteration of the SSE instruction set for the IA-32 architecture x86-64 is a Superset of the x86 instruction set architecture. Cool'n'Quiet is a CPU speed throttling and power saving technology introduced by AMD with their Athlon 64 processor line The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (or code Socket 939 is a CPU socket released by AMD in June 2004 to supersede the previous Socket 754 for Athlon 64 processors 35/1. 4 V
- First release: October 2005
- Clockrate: 1800–2000 MHz
- 128 KiB L2-Cache (Sempron 3000+, 3400+)
- 256 KiB L2-Cache (Sempron 3200+, 3500+)
- Steppings: E3 (Part No. : *BP), E6 (Part No. : *BW)
Models for Socket AM2
Manila (90 nm SOI)
- L1-Cache: 64 + 64 KiB (Data + Instructions)
- L2-Cache: 128/256 KiB, fullspeed
- MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit
- Integrated 128-bit(Dual channel) DDR2 memory controller
- Socket AM2, 800 MHz HyperTransport
- VCore: 1. MMX is a single instruction multiple data (SIMD Instruction set designed by Intel, introduced in 1997 in their Pentium line of 3DNow! is the Trade name of a multimedia extension created by AMD for its processors starting with the K6-2 in 1998 S treaming '''S'''IMD E xtensions ( SSE) is a SIMD (Single Instruction Multiple Data Instruction set extension to the X86 SSE2, Streaming SIMD Extensions 2, is one of the IA-32 SIMD (Single Instruction Multiple Data Instruction sets SSE2 was first introduced by SSE3, also known by its Intel code name Prescott New Instructions (PNI, is the third iteration of the SSE instruction set for the IA-32 architecture x86-64 is a Superset of the x86 instruction set architecture. Cool'n'Quiet is a CPU speed throttling and power saving technology introduced by AMD with their Athlon 64 processor line The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (or code The Socket AM2, renamed from Socket M2 (to prevent using the same name as Cyrix MII processors is a CPU socket designed by AMD for desktop 25/1. 35/1. 40 V (1. 20/1. 25 V for Energy Efficient SFF version)
- First release: May 23, 2006
- Clockrate: 1600–2000 MHz
- 128 KiB L2-Cache (Sempron 2800+, 3200+, 3500+)
- 256 KiB L2-Cache (Sempron 3000+, 3400+, 3600+, 3800+)
- Stepping: F2 (Part No. Events 1430 - Siege of Compiègne: Joan of Arc is captured by the Burgundians while leading an army to relieve Compiègne Year 2006 ( MMVI) was a Common year starting on Sunday of the Gregorian calendar. : *CN, *CW)
Sparta (65 nm SOI)

- L1-Cache: 64 + 64 KiB (Data + Instructions)
- L2-Cache: 256/512 KiB, fullspeed
- MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit
- Integrated 128-bit(Dual channel) DDR2 memory controller
- Socket AM2, 800 MHz HyperTransport
- VCore: 1. MMX is a single instruction multiple data (SIMD Instruction set designed by Intel, introduced in 1997 in their Pentium line of 3DNow! is the Trade name of a multimedia extension created by AMD for its processors starting with the K6-2 in 1998 S treaming '''S'''IMD E xtensions ( SSE) is a SIMD (Single Instruction Multiple Data Instruction set extension to the X86 SSE2, Streaming SIMD Extensions 2, is one of the IA-32 SIMD (Single Instruction Multiple Data Instruction sets SSE2 was first introduced by SSE3, also known by its Intel code name Prescott New Instructions (PNI, is the third iteration of the SSE instruction set for the IA-32 architecture x86-64 is a Superset of the x86 instruction set architecture. Cool'n'Quiet is a CPU speed throttling and power saving technology introduced by AMD with their Athlon 64 processor line The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (or code The Socket AM2, renamed from Socket M2 (to prevent using the same name as Cyrix MII processors is a CPU socket designed by AMD for desktop 20/1. 40 V
- First release: August 20, 2007
- Clockrate: 1900–2300 MHz
- 256 KiB L2-Cache (Sempron LE-1100, LE-1150)
- 512 KiB L2-Cache (Sempron LE-1250, LE-1300)
- Stepping: G1 (Part No. Events 636 - Battle of Yarmouk: Arab forces led by Khalid ibn al-Walid take control of Syria and Palestine Year 2007 ( MMVII) was a Common year starting on Monday of the Gregorian calendar in the 21st century. : *DE), G2 (Part No. : *DP)
Models for Socket S1 (638)
Keene (90 nm SOI)
- L1-Cache: 64 + 64 KiB (Data + Instructions)
- L2-Cache: 256 or 512 KiB, fullspeed
- MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit
- Integrated 128-bit(Dual channel) DDR2 memory controller
- Socket S1, 800 MHz HyperTransport
- VCore: 0. MMX is a single instruction multiple data (SIMD Instruction set designed by Intel, introduced in 1997 in their Pentium line of 3DNow! is the Trade name of a multimedia extension created by AMD for its processors starting with the K6-2 in 1998 S treaming '''S'''IMD E xtensions ( SSE) is a SIMD (Single Instruction Multiple Data Instruction set extension to the X86 SSE2, Streaming SIMD Extensions 2, is one of the IA-32 SIMD (Single Instruction Multiple Data Instruction sets SSE2 was first introduced by SSE3, also known by its Intel code name Prescott New Instructions (PNI, is the third iteration of the SSE instruction set for the IA-32 architecture x86-64 is a Superset of the x86 instruction set architecture. Cool'n'Quiet is a CPU speed throttling and power saving technology introduced by AMD with their Athlon 64 processor line The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (or code Socket S1 is the CPU socket type used by AMD for their Turion 64, Athlon 64 Mobile and later Sempron processors which debuted 950-1. 25 V
- First release: May 17, 2006
- Clockrate: 1000–2000 MHz
- 256 KiB L2-Cache (Sempron 2100+, 3400+)
- 512 KiB L2-Cache (Sempron 3200+, 3500+, 3600+)
- Stepping: F2 (Part No. Events 1521 - Edward Stafford 3rd Duke of Buckingham, is executed for Treason. Year 2006 ( MMVI) was a Common year starting on Sunday of the Gregorian calendar. : *CM)
Socket 754 32-bit Semprons
| Max P-State |
Model |
Manufacturing Process |
Part Number(OPN) |
| 1600 MHz |
2600+ |
0. 09 micrometre |
SDA2600AIO2BA(some parts are 64-bit) |
| 1600 MHz |
2800+ |
0. 09 micrometre |
SDA2800AIO3BA |
| 1800 MHz |
3000+ |
0. 13 micrometre |
SDA3000AIP2AX |
| 1800 MHz |
3100+ |
0. 13 micrometre |
SDA3100AIP3AX |
| 1800 MHz |
3100+ |
0. 09 micrometre |
SDA3100AIO3BA |
| 2000 MHz |
3300+ |
0. 09 micrometre |
SDA3300AIO2BA |
Socket S1 (638) 64-bit Semprons
| Max P-State |
Model |
Manufacturing Process |
Part Number(OPN) |
| 1000 MHz |
800 |
0. 09 micrometre |
TBA |
| 1600 MHz |
3200 |
0. 09 micrometre |
SMS3200HAX4CM |
| 1800 MHz |
3400 |
0. 09 micrometre |
SMS3400HAX3CM |
| 1800 MHz |
3500 |
0. 09 micrometre |
SMS3500HAX4CM |
| 2000 MHz |
3600 |
0. 09 micrometre |
SMS3600HAX3CM |
AMD has released some Sempron processors without Cool'n'Quiet support. Cool'n'Quiet is a CPU speed throttling and power saving technology introduced by AMD with their Athlon 64 processor line The following table describes those processors lacking Cool'n'Quiet.
| Max P-State |
Min P-State |
Model |
Operating Mode |
Package-Socket |
Manufacturing Process |
Part Number(OPN) |
| 1400 MHz |
N/A |
2500+ |
32/64 |
Socket 754 |
0. 09 micrometre |
SDA2500AIO3BX |
| 1600 MHz |
N/A |
2600+ |
32 or 32/64 |
Socket 754 |
0. 09 micrometre |
SDA2600AIO2BA |
| 1600 MHz |
N/A |
2600+ |
32/64 |
Socket 754 |
0. 09 micrometre |
SDA2600AIO2BX |
| 1600 MHz |
N/A |
2800+ |
32 |
Socket 754 |
0. 09 micrometre |
SDA2800AIO3BA |
| 1600 MHz |
N/A |
2800+ |
32/64 |
Socket 754 |
0. 09 micrometre |
SDA2800AIO3BX |
| 1600 MHz |
N/A |
2800+ |
32/64 |
Socket AM2 |
0. 09 micrometre |
SDA2800IAA2CN |
| 1600 MHz |
N/A |
3000+ |
32/64 |
Socket AM2 |
0. 09 micrometre |
SDA3000IAA3CN |
| 1600 MHz |
N/A |
3000+ |
32/64 |
Socket AM2 |
0. 09 micrometre |
SDD3000IAA3CN |
Future plans
In 2008, Sempron-branded implementations of the Stars microarchitecture are expected to become available, based on the Rana core. The AMD K10 is AMD 's latest Microprocessor architecture. Though there were once reports that the K10 had been cancelled, the first third-generation These are expected to be dual-core processors without L3 cache. Initial clock rates will be between 2. 1 GHz and 2. 3 GHz. The Rana Semprons will feature HyperTransport 3. 0 support and will be packaged for the Socket AM2+ form factor, although they are expected to function in Socket AM2 motherboards, albeit without support for HyperTransport 3. Socket AM2+ is a CPU socket, which is the immediate successor to Socket AM2 that is currently used by several AMD Processors such as Athlon The Socket AM2, renamed from Socket M2 (to prevent using the same name as Cyrix MII processors is a CPU socket designed by AMD for desktop 0 enhancements. [2]
References
See also
External links
The Sempron is AMD's newest low-end CPU replacing the Duron processor
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