OpenRISC is an open source hardware RISC CPU design by OpenCores released under the GNU Lesser General Public License. Open source is a development methodology which offers practical accessibility to a product's source (goods and knowledge Open source hardware refers to computer and electronic hardware that is designed in the same fashion as free and open-source Software. OpenCores is a loose community of people who are interested in developing Digital Open source hardware through Electronic design automation, with a similar The GNU Lesser General Public License (formerly the GNU Library General Public License) or LGPL is a Free software license published by the Free Software The OpenCores team implemented the design in the verilog hardware description language. In the Semiconductor and electronic design industry Verilog is a Hardware description language (HDL used to model electronic systems. In Electronics, a hardware description language or HDL is any language from a class of Computer languages and/or Programming languages for formal Flextronics International and Jennic Ltd. manufactured the OpenRISC as part of an ASIC. Others implemented OpenRISC in a FPGA. FPGAs should not be confused with the Flip-chip pin grid array, a form of integrated circuit packaging
The OpenCores team also ported the GNU toolchain to OpenRISC to support development in several languages. The GNU toolchain is a blanket term for a collection of Programming tools produced by the GNU Project. Linux and µClinux have been ported to the processor. Linux (commonly pronounced ˈlɪnəks
See also
External links
- OpenRISC 1200 at the Open Cores Website
- GNU toolchain building guides
- Beyond Semiconductor commercial fabless semiconductor company founded by the developers of OpenRISC
- Dynalith Systems provides hardware and software solutions for OpenRISC. LEON is a Computer CPU core specifically a 32-bit Microprocessor based on RISC design OpenSPARC is an Open source hardware project started in December 2005 S1 Core (codename Sirocco) is an Open source hardware Microprocessor design developed by Simply RISC. LatticeMico32 is a 32-bit Microprocessor soft core from Lattice Semiconductor optimized for Field Programmable Gate Arrays ( FPGAs. A fabless semiconductor company specializes in the design and sale of Hardware devices implemented on Semiconductor
- Dynalith Systems provides ICE for OpenRISC, which connects GDB server to Debug Unit through JTAG and is based on USB 2. 0.
- IMPERAS MULTI-CORE SOFTWARE DEVELOPMENT TOOLS, MP development and debug tools for virtual platforms running at 100s of MIPS for ARM, MIPS, Tensilica, OpenRISC, and proprietary processors. Instructions per second (IPS is a measure of a Computer 's processor speed
- Open Virtual Platforms' OVPsim 500 mips OR1K emulator, enables you to develop software on your PC using virtual platforms, emulators including OpenCores processors running at up to 500 MIPS for OR1K processors running many OSes including ucLinux. Instructions per second (IPS is a measure of a Computer 's processor speed OVP is used to build emulators of single OR1K processors or multiple - homogeneous MP or heterogenous MP. See: www.OVPworld.org
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