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Diagram of a generic dual core processor, with CPU-local Level 1 caches, and a shared, on-die Level 2 cache.
Diagram of a generic dual core processor, with CPU-local Level 1 caches, and a shared, on-die Level 2 cache.
Intel Core 2 Duo E6750 is a dual core processor
Intel Core 2 Duo E6750 is a dual core processor
AMD Athlon X2 6400+ is a dual core processor
AMD Athlon X2 6400+ is a dual core processor

A multi-core CPU (or chip-level multiprocessor, CMP) combines two or more independent cores into a single package composed of a single integrated circuit (IC), called a die, or more dies packaged together. The Core 2 brand refers to a range of Intel 's consumer 64-bit dual-core and 2x2 MCM quad-core CPUs with the X86-64 instruction set The Athlon 64 X2 is the first dual-core desktop CPU manufactured by AMD. Microchipsjpg|right|thumb|200px|Microchips ( EPROM memory with a transparent window showing the integrated circuit inside A dual-core processor contains two cores and a quad-core processor contains four cores. A multi-core microprocessor implements multiprocessing in a single physical package. Multiprocessing is the use of two or more central processing units (CPUs within a single computer system A processor with all cores on a single die is called a monolithic processor. Cores in a multicore device may share a single coherent cache at the highest on-device cache level (e. In Computer science, a cache (kæʃ like "cash") is a collection of data duplicating original g. L2 for the Intel Core 2) or may have separate caches (e. g. current AMD dual-core processors). The processors also share the same interconnect to the rest of the system. Each "core" independently implements optimizations such as superscalar execution, pipelining, and multithreading. A superscalar CPU architecture implements a form of parallelism called Instruction-level parallelism within a single processor In Computing, a pipeline is a set of data processing elements connected in series so that the output of one element is the input of the next one Multithreading computers have hardware support to efficiently execute multiple threads. A system with n cores is effective when it is presented with n or more threads concurrently. A thread in Computer science is short for a thread of execution. The most commercially significant (or at least the most 'obvious') multi-core processors are those used in personal computers (primarily from Intel & AMD) and game consoles (e. A personal computer ( PC) is any Computer whose original sales price size and capabilities make it useful for individuals and which is intended to be operated g. , the 8 core Cell processor in the PS3 and the 3 core Xenon processor in the Xbox 360). Cell is a Microprocessor architecture jointly developed by Sony Computer Entertainment, Toshiba, and IBM, an Xenon is a CPU that is used in the Xbox 360 game console The processor internally codenamed "Waternoose" by IBM and "XCPU" The Xbox 360 is the second Video game console produced by Microsoft, and was developed in cooperation with IBM, ATI, and SiS. In this context, "multi" typically means a relatively small number of cores. However, the technology is widely used in other technology areas, especially those of embedded processors, such as network processors and digital signal processors, and in GPUs. An embedded system is a special-purpose Computer system designed to perform one or a few dedicated functions often with Real-time computing constraints A network processor is an Integrated circuit which has a feature set specifically targeted at the networking application domain A digital signal processor ( DSP or DSP micro) is a specialized Microprocessor designed specifically for Digital signal processing, generally

The amount of performance gained by the use of a multicore processor depends on the problem being solved and the algorithms used, as well as their implementation in software (Amdahl's law). Amdahl's law, also known as Amdahl's argument, is named after computer architect Gene Amdahl, and is used to find the maximum expected improvement For so-called "embarrassingly parallel" problems, a dual-core processor with two cores at 2GHz may perform very nearly as fast as a single core of 4GHz. In the jargon of Parallel computing, an embarrassingly parallel workload (or embarrassingly parallel problem is one for which no particular effort is needed to segment the problem [1] Other problems though may not yield so much speedup. This all assumes however that the software has been designed to take advantage of available parallelism. If it hasn't, there will not be any speedup at all. However, the processor will multitask better since it can run two programs at once, one on each core.

Contents

Terminology

There is some discrepancy in the semantics by which the terms multi-core and dual-core are defined. Semantics is the study of meaning in communication The word derives from Greek σημαντικός ( semantikos) "significant" from Most commonly they are used to refer to some sort of central processing unit (CPU), but are sometimes also applied to digital signal processors (DSP) and System-on-a-chip (SoC). A digital signal processor ( DSP or DSP micro) is a specialized Microprocessor designed specifically for Digital signal processing, generally System-on-a-chip or system on chip ( SoC or SOC) refers to integrating all components of a Computer or other electronic System Additionally, some use these terms only to refer to multi-core microprocessors that are manufactured on the same integrated circuit die. A die in the context of Integrated circuits is a small block of semiconducting material on which a given functional circuit is fabricated These people generally refer to separate microprocessor dies in the same package by another name, such as multi-chip module, double core, or even twin core. A Multi-Chip Module (MCM is a specialized electronic package where multiple Integrated circuits (ICs semiconductor dies or other modules are packaged in such a way as This article uses both the terms "multi-core" and "dual-core" to reference microelectronic CPUs manufactured on the same integrated circuit, unless otherwise noted.

In contrast to multi-core systems, the term multi-CPU refers to multiple physically separate processing units (which often contain special circuitry to facilitate communication between each other).

Development

While manufacturing technology continues to improve, reducing the size of single gates, physical limits of semiconductor-based microelectronics have become a major design concern. Some effects of these physical limitations can cause significant heat dissipation and data synchronization problems. The demand for more capable microprocessors causes CPU designers to use various methods of increasing performance. Some instruction-level parallelism (ILP) methods like superscalar pipelining are suitable for many applications, but are inefficient for others that tend to contain difficult-to-predict code. Instruction-level parallelism (ILP is a measure of how many of the operations in a Computer program can be performed simultaneously A superscalar CPU architecture implements a form of parallelism called Instruction-level parallelism within a single processor In Computing, a pipeline is a set of data processing elements connected in series so that the output of one element is the input of the next one Many applications are better suited to thread level parallelism (TLP) methods, and multiple independent CPUs is one common method used to increase a system's overall TLP. A combination of increased available space due to refined manufacturing processes and the demand for increased TLP is the logic behind the creation of multi-core CPUs.

Commercial incentives

Several business motives drive the development of dual-core architectures. Since symmetric multiprocessing (SMP) designs have been long implemented using discrete CPUs, the issues regarding implementing the architecture and supporting it in software are well known. In Computing, symmetric multiprocessing or SMP involves a Multiprocessor computer-architecture where two or more identical processors can connect to a single Additionally, utilizing a proven processing core design (e. g. Freescale's e600 core) without architectural changes reduces design risk significantly. Finally, the terminology "dual-core" (and other multiples) lends itself to marketing efforts.

Additionally, for general-purpose processors, much of the motivation for multi-core processors comes from greatly diminished gains in processor performance from increasing the operating frequency (frequency scaling). Frequency scaling (also known as frequency ramping) is in Computer architecture, the technique of ramping a processor's Frequency so as to achieve The memory wall and the ILP wall are the culprits in why system performance has not gained as much from continued processor frequency increases as was once seen. The memory wall refers to the increasing gap between processor and memory speeds, which pushes cache sizes larger to mask the latency to memory which helps only to the extent that memory bandwidth is not the bottleneck in performance. The ILP wall refers to increasing difficulty to find enough parallelism in the instructions stream of a single process to keep higher performance processor cores busy. Finally, the often cited, power wall refers to the trend of consuming double the power with each doubling of operating frequency (which is possible to contain to just doubling only if the processor is made smaller). The power wall poses manufacturing, system design and deployment problems that have not been justified in the face of the diminished gains in performance due to the memory wall and ILP wall. Together, these three walls combine to motivate multicore processors.

In order to continue delivering regular performance improvements for general-purpose processors, manufacturers such as Intel and AMD have turned to multi-core designs, sacrificing lower manufacturing costs for higher performance in some applications and systems.

Multi-core architectures are being developed, but so are the alternatives. An especially strong contender for established markets is to integrate more peripheral functions into the chip.

Advantages

The proximity of multiple CPU cores on the same die allows the cache coherency circuitry to operate at a much higher clock rate than is possible if the signals have to travel off-chip. In computing Cache coherency (also cache coherence) refers to the integrity of data stored in local caches of a shared resource Combining equivalent CPUs on a single die significantly improves the performance of cache snoop (alternative: Bus snooping) operations. Bus sniffing or Bus snooping is a technique used in Distributed shared memory systems and multiprocessors aimed at achieving Cache coherence. Bus sniffing or Bus snooping is a technique used in Distributed shared memory systems and multiprocessors aimed at achieving Cache coherence. Put simply, this means that signals between different CPUs travel shorter distances, and therefore those signals degrade less. A discrete signal or discrete-time signal is a Time series, perhaps a signal that has been sampled from a continuous-time signal. In Telecommunication, degradation, which may be categorized as either " graceful " or " catastrophic " has the following meanings These higher quality signals allow more data to be sent in a given time period since individual signals can be shorter and do not need to be repeated as often.

Assuming that the die can fit into the package, physically, the multi-core CPU designs require much less Printed Circuit Board (PCB) space than multi-chip SMP designs. A printed circuit board, or PCB, is used to mechanically support and electrically connect Electronic components using conductive pathways or traces Also, a dual-core processor uses slightly less power than two coupled single-core processors, principally because of the increased power required to drive signals external to the chip and because the smaller silicon process geometry allows the cores to operate at lower voltages; such reduction reduces latency. Furthermore, the cores share some circuitry, like the L2 cache and the interface to the front side bus (FSB). In Personal computers the Front Side Bus ( FSB) is the bus that carries data between the CPU and the northbridge. In terms of competing technologies for the available silicon die area, multi-core design can make use of proven CPU core library designs and produce a product with lower risk of design error than devising a new wider core design. Also, adding more cache suffers from diminishing returns.

Disadvantages

In addition to operating system (OS) support, adjustments to existing software are required to maximize utilization of the computing resources provided by multi-core processors. An operating system (commonly abbreviated OS and O/S) is the software component of a Computer system that is responsible for the management and coordination Also, the ability of multi-core processors to increase application performance depends on the use of multiple threads within applications. The situation is improving: for example the American PC game developer Valve Corporation has stated that it will use multi core optimizations for the next version of its Source engine, shipped with Half-Life 2: Episode Two, the next installment of its Half-Life franchise[2][3], and Crytek is developing similar technologies for CryEngine 2, which powers their game, Crysis. The United States of America —commonly referred to as the A video game developer is a software developer (a business or an individual that creates Video games A developer may specialize in a certain video Valve Corporation is an American video game development company based in Bellevue Washington, USA that was founded in 1996, and made famous The Source engine is a 3D game engine developed by Valve Corporation. Half-Life 2 Episode Two is the second installment in Valve Corporation 's series of episodes for the First person shooter Computer game Crytek is a German Video game company founded in 1999 by three Turkish-German brothers Cevat Avni and Faruk Yerli CryEngine2 is a Game engine. It is an extended version of the CryEngine, the game engine behind Far Cry. CRYSIS is an acronym for CRY ogenic S tockholm I on S ource CRYSIS is an Ion source of EBIS type and is located in Stockholm Emergent Game Technologies' Gamebryo engine includes their Floodgate technology[4] which simplifies multicore development across game platforms. Emergent Game Technologies was founded in 2002 and develops Middleware technologies for building testing managing and expanding Video games. Gamebryo is computer and video games middleware, originally from Numerical Design Limited (NDL and is the successor to NDL's NetImmerse engine See Dynamic Acceleration Technology for the Santa Rosa platform for an example of a technique to improve single-thread performance on dual-core processors. Centrino is a platform- Marketing initiative from Intel. It is not a mobile CPU - rather the term covers a particular combination of mainboard Chipset

Integration of a multi-core chip drives production yields down and they are more difficult to manage thermally than lower-density single-chip designs. Intel has partially countered this first problem by creating its quad-core designs by combining two dual-core on a single die with a unified cache, hence any two working dual-core dies can be used, as opposed to producing four cores on a single die and requiring all four to work to produce a quad-core. From an architectural point of view, ultimately, single CPU designs may make better use of the silicon surface area than multiprocessing cores, so a development commitment to this architecture may carry the risk of obsolescence. Finally, raw processing power is not the only constraint on system performance. Two processing cores sharing the same system bus and memory bandwidth limits the real-world performance advantage. If a single core is close to being memory bandwidth limited, going to dual-core might only give 30% to 70% improvement. If memory bandwidth is not a problem, a 90% improvement can be expected. It would be possible for an application that used 2 CPUs to end up running faster on one dual-core if communication between the CPUs was the limiting factor, which would count as more than 100% improvement.

Hardware trend

The general trend in processor development has been from multi-core to many-core: from dual-, quad-, eight-core chips to ones with tens or even hundreds of cores; see manycore processing unit. A many-core processing unit is a type of Microprocessor -based system characterized by multiple standard Instruction set Microprocessor In addition, multi-core chips mixed with simultaneous multithreading, memory-on-chip, and special-purpose "heterogeneous" cores promise further performance and efficiency gains, especially in processing multimedia, recognition and networking applications. Simultaneous multithreading, often abbreviated as SMT, is a technique for improving the overall efficiency of Superscalar CPUs with Hardware There is also a trend of improving energy efficiency by focusing on performance-per-watt with advanced fine-grain or ultra fine-grain power management and dynamic voltage and frequency scaling (DVFS), which is of particular interest for mobile computing (i. Power management is a feature of some electrical appliances especially copiers, computers and computer Peripherals such as monitors and Mobile computing is a generic term describing one's ability to use technology while moving as opposed to Portable computers which are only practical for use while deployed in e. laptop computers and portable media players). A laptop computer, also known as a notebook computer, is a small Personal computer designed for mobile use. A portable multimedia player ( PMP) sometimes referred to as a portable video player ( PVP) is a Consumer electronics device that is capable

Software impact

Software benefits from multicore architectures where code can be executed in parallel. Under most common operating systems this requires code to execute in separate threads or processes. A thread in Computer science is short for a thread of execution. In computing a process is an instance of a Computer program that is being sequentially executed by a computer system that has the ability to run several computer Each application running on a system runs in its own process so multiple applications will benefit from multicore architectures. Each application may also have multiple threads but, in most cases, it must be specifically written to utilize multiple threads. Operating system software also tends to run many threads as a part of its normal operation. Running virtual machines will benefit from adoption of multiple core architectures since each virtual machine runs independently of others and can be executed in parallel. In Computer science, a virtual machine (VM is a Software implementation of a machine (computer that executes programs like a real machine

Most application software is not written to use multiple concurrent threads intensively because of the challenge of doing so. A frequent pattern in multithreaded application design is where a single thread does the intensive work while other threads do much less. For example, a virus scan application may create a new thread for the scan process, while the GUI thread waits for commands from the user (e. g. cancel the scan). In such cases, multicore architecture is of little benefit for the application itself due to the single thread doing all heavy lifting and the inability to balance the work evenly across multiple cores. Programming truly multithreaded code often requires complex co-ordination of threads and can easily introduce subtle and difficult-to-find bugs due to the interleaving of processing on data shared between threads (thread-safety). Thread safety is a Computer programming concept applicable in the context of Multi-threaded programs Consequently, such code is much more difficult to debug than single-threaded code when it breaks. There has been a perceived lack of motivation for writing consumer-level threaded applications because of the relative rarity of consumer-level multiprocessor hardware. Although threaded applications incur little additional performance penalty on single-processor machines, the extra overhead of development has been difficult to justify due to the preponderance of single-processor machines.

As of September 2006, with the typical mix of mass-market applications the main benefit to an ordinary user from a multi-core CPU will be improved multitasking performance, which may apply more often than expected. Ordinary users are already running many threads; operating systems utilize multiple threads, as well as antivirus programs and other 'background processes' including audio and video controls. The largest boost in performance will likely be noticed in improved response time while running CPU-intensive processes, like antivirus scans, defragmenting, ripping/burning media (requiring file conversion), or searching for folders. For example, if the automatic virus scan initiates while a movie is being watched, the movie is far less likely to lag, as the antivirus program will be assigned to a different processor than the processor running the movie playback.

Given the increasing emphasis on multicore chip design, stemming from the grave thermal and power consumption problems posed by any further significant increase in processor clock speeds, the extent to which software can be multithreaded to take advantage of these new chips is likely to be the single greatest constraint on computer performance in the future. If developers are unable to design software to fully exploit the resources provided by multiple cores, then they will ultimately reach an insurmountable performance ceiling.

The telecommunications market had been one of the first that needed a new design of parallel datapath packet processing because there was a very quick adoption of these multiple core processors for the datapath and the control plane. These MPUs are going to replace the traditional Network Processors that were based on proprietary micro- or pico- code. 6WIND was the first company to provide embedded software for these applications.

Parallel programming techniques can benefit from multiple cores directly. Parallel computing is a form of computation in which many instructions are carried out simultaneously operating on the principle that large problems can often Some existing parallel programming models such as Cilk++, OpenMP and MPI can be used on multi-core platforms. A parallel programming model is a set of software technologies to express Parallel algorithms and match applications with the underlying parallel systems The OpenMP (Open Multi-Processing is an Application programming interface (API that supports multi-platform Shared memory Multiprocessing programming Message Passing Interface ( MPI) is a specification for an API that allows many computers to communicate with one another Intel introduced a new abstraction for C++ parallelism called TBB. Intel Threading Building Blocks (also known as TBB) is the name of a C++ template library developed by Intel for writing software Other research efforts include the Codeplay Sieve System, Cray's Chapel, Sun's Fortress, and IBM's X10. The Sieve C++ Parallel Programming System is a C++ Compiler and parallel runtime designed and released by Codeplay that aims to simplify the parallelization Chapel is a new parallel Programming language being developed by Cray Inc Fortress is a draft specification for a Programming language, initially developed by Sun Microsystems as part of a DARPA -funded Supercomputing X10 is a Programming language being developed by IBM at the Thomas J

Managing concurrency acquires a central role in developing parallel applications. Concurrent computing is the concurrent (simultaneous execution of multiple interacting computational tasks The basic steps in designing parallel applications are:

Partitioning 
The partitioning stage of a design is intended to expose opportunities for parallel execution. Hence, the focus is on defining a large number of small tasks in order to yield what is termed a fine-grained decomposition of a problem.
Communication 
The tasks generated by a partition are intended to execute concurrently but cannot, in general, execute independently. The computation to be performed in one task will typically require data associated with another task. Data must then be transferred between tasks so as to allow computation to proceed. This information flow is specified in the communication phase of a design.
Agglomeration 
In the third stage, we move from the abstract toward the concrete. We revisit decisions made in the partitioning and communication phases with a view to obtaining an algorithm that will execute efficiently on some class of parallel computer. In particular, we consider whether it is useful to combine, or agglomerate, tasks identified by the partitioning phase, so as to provide a smaller number of tasks, each of greater size. We also determine whether it is worthwhile to replicate data and/or computation.
Mapping 
In the fourth and final stage of the parallel algorithm design process, we specify where each task is to execute. This mapping problem does not arise on uniprocessors or on shared-memory computers that provide automatic task scheduling.

On the other hand, on the server side, multicore processors are ideal because they allow many users to connect to a site simultaneously and have independent threads of execution. Server-side refers to operations that are performed by the server in a Client-server relationship in Computer networking. A thread in Computer science is short for a thread of execution. This allows for Web servers and application servers that have much better throughput. In Communication networks, such as Ethernet or Packet radio, throughput is the average rate of successful message delivery over a communication channel

Licensing

Typically, proprietary enterprise server software is licensed "per processor". In the past a CPU was a processor and most computers had only one CPU, so there was no ambiguity.

Now there is the possibility of counting cores as processors and charging a customer for multiple licenses for a multi-core CPU. However, the trend seems to be counting dual-core chips as a single processor as Microsoft, Intel, and AMD support this view. Microsoft have said they would treat a socket as a single processor[5].

Oracle counts an AMD or Intel dual-core CPU as a single processor but has other numbers for other types, especially for processors with more than 2 cores. IBM, HP and Microsoft count a multi-chip module as multiple processors. If multi-chip modules count as one processor, CPU makers have an incentive to make large expensive multi-chip modules so their customers save on software licensing. So it seems that the industry is slowly heading towards counting each die (see Integrated circuit) as a processor, no matter how many cores each die has. Microchipsjpg|right|thumb|200px|Microchips ( EPROM memory with a transparent window showing the integrated circuit inside Intel has released Paxville which is really a multi-chip module but Intel is calling it a dual-core - because it uses only one socket. It is not clear yet how licensing will work for Paxville. This is an unresolved and thorny issue for software companies and customers of proprietary software, leading many to consider open source alternative. Open source is a development methodology which offers practical accessibility to a product's source (goods and knowledge

Embedded Applications

A distinct area of processor technology from "mainstream" PCs is that of embedded computing. An embedded system is a special-purpose Computer system designed to perform one or a few dedicated functions often with Real-time computing constraints The same technological drivers towards multicore apply here too. Indeed, in many cases the application is a "natural" fit for multicore technologies, if the task can easily be partitioned between the different processors.

In network processing, it is now mainstream for devices to be multi-core, with companies such as Cavium Networks, Wintegra and Broadcom all manufacturing products with eight processors. A network processor is an Integrated circuit which has a feature set specifically targeted at the networking application domain Cavium Networks ( is a Mountain View California -based company specializing in ARM -based and MIPS -based network and security processors Broadcom Corporation is an American supplier of Integrated circuits (ICs for broadband communications In digital signal processing the same trend applies: Texas Instruments has the three-core TMS320C6488, Freescale the four-core MSC8144 (and both have stated they are working on eight-core successors). Digital signal processing ( DSP) is concerned with the representation of the signals by a sequence of numbers or symbols and the processing of these signals Texas Instruments ( better known in the electronics industry (and popularly as TI, is an American company based in Dallas, Texas, USA Freescale Semiconductor Inc is an American Semiconductor manufacturer Newer entries include the Storm-1 family from Stream Processors, Inc with 40 and 80 general purpose ALUs per chip, all programmable in C as a SIMD engine and Picochip with three-hundred processors on a single die, focused on communication applications. picoChip is a venture-backed Fabless semiconductor company based in Bath England, founded in 2000

Commercial examples

Hardware

Integrated circuit of Atmel Diopsis 740
Integrated circuit of Atmel Diopsis 740

Software

Notes

  1. ^  Digital signal processors, DSPs, have utilized multi-core architectures for much longer than high-end general purpose processors. A digital signal processor ( DSP or DSP micro) is a specialized Microprocessor designed specifically for Digital signal processing, generally A typical example of a DSP-specific implementation would be a combination of a RISC CPU and a DSP MPU. This allows for the design of products that require a general purpose processor for user interfaces and a DSP for real-time data processing; this type of design is common in mobile phones. In other applications, a growing number of companies have developed multi-core DSPs with very large numbers of processors.
  2. ^  Two types of operating systems are able to utilize a dual-CPU multiprocessor: partitioned multiprocessing and symmetric multiprocessing (SMP). An operating system (commonly abbreviated OS and O/S) is the software component of a Computer system that is responsible for the management and coordination In Computing, symmetric multiprocessing or SMP involves a Multiprocessor computer-architecture where two or more identical processors can connect to a single In a partitioned architecture, each CPU boots into separate segments of physical memory and operate independently; in an SMP OS, processors work in a shared space, executing threads within the OS independently.

See also

References

  1. ^ http://www.alienware.com/intro_pages/processors_101.aspx
  2. ^ Multi-core in the Source Engine
  3. ^ AMD: dual-core not for gamers... yet
  4. ^ Gamebryo's Floodgate page
  5. ^ Multicore Processor Licensing
  6. ^ 80-core prototype from Intel

External links

BMDFM (Binary Modular Dataflow Machine is software which enables running an application in parallel on shared memory symmetric multiprocessors ( SMP) using the multiple
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