The memory controller is a chip on a computer's motherboard or CPU die which manages the flow of data going to and from the memory. A motherboard is the central or primary Printed circuit board (PCB making up a complex electronic system such as a modern Computer or Laptop
Most computers based on an Intel processor have a memory controller implemented on their motherboard's northbridge, though some modern microprocessors, such as AMD's Athlon 64 and Opteron processors, IBM's POWER5, and Sun Microsystems UltraSPARC T1 have a memory controller on the CPU die to reduce the memory latency. The northbridge, also known as the memory controller hub ( MCH) in Intel systems (AMD VIA SiS and others usually use 'northbridge' is traditionally one A microprocessor incorporates most or all of the functions of a Central processing unit (CPU on a single Integrated The Athlon 64 is an eighth-generation AMD64 architecture Microprocessor produced by AMD, released on The Opteron is AMD 's X86 server processor line and was the first processor to implement the AMD64 Instruction set architecture (known International Business Machines Corporation abbreviated IBM and nicknamed "Big Blue", is a multinational Computer Technology POWER5 is a Microprocessor developed by IBM. It is an improved variant of the highly successful POWER4. Sun Microsystems Inc ( is a multinational vendor of Computers computer components Computer software, and Information technology services Sun Microsystems ' UltraSPARC T1 Microprocessor, known until its 14 November 2005 announcement by its development Codename " In Computing, memory latency is the time between initiating a request for a Byte or word in memory until it is retrieved While this has the potential to increase the system's performance, it locks the processor to a specific type (or types) of memory, forcing a redesign in order to support newer memory technologies. When DDR2 SDRAM was introduced, AMD released new Athlon 64 CPUs. These new models, with a DDR2 controller, use a different physical socket (known as Socket AM2), so that they will only fit in motherboards designed for the new type of RAM. The Socket AM2, renamed from Socket M2 (to prevent using the same name as Cyrix MII processors is a CPU socket designed by AMD for desktop When the memory controller is not on-die, the same CPU may be installed on a new motherboard, with an updated northbridge.
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Purpose
Memory controllers contain the logic necessary to read and write dynamic RAM, and to "refresh" the DRAM by sending current through the entire device. Without constant refreshes, DRAM will lose the data written to it as the capacitors leak their charge within a number of milliseconds (64 milliseconds according to JEDEC standards). A capacitor is a passive electrical component that can store Energy in the Electric field between a pair of conductors JEDEC Solid State Technology Association, formerly known as J oint E lectron D evice E ngineering C ouncil ( JEDEC) or Joint
Reading and writing to DRAM is facilitated by use of multiplexers and demultiplexers, by selecting the correct row and column address as the inputs to the multiplexer circuit, where the demultiplexer on the DRAM can select the correct memory location and return the data (once again passed through a multiplexer to reduce the number of wires necessary to assemble the system). In Electronics, a multiplexer or mux ( occasionally the term muldex is also found for a combination multiplexer-demultiplexer In Electronics, a multiplexer or mux ( occasionally the term muldex is also found for a combination multiplexer-demultiplexer
Bus width is the measure of how many parallel lanes of traffic are available to communicate with the memory cell. Memory controllers bus width ranges from 8-bit in earlier systems, to 256-bit in more complicated systems and video cards (typically implemented as four, 64-bit simultaneous memory controllers operating in parallel, though some are designed to operate in "gang mode" where two 64-bit memory controllers can be used to access a 128-bit memory device). Eight-bit CPUs normally use an 8-bit data bus and a 16-bit address bus which means that their Address space is limited to 64 KBs This is not a "natural '64-bit' CPUs have existed in Supercomputers since the 1960s and in RISC -based workstations and servers since the early 1990s.
Double data rate memory
Double Data Rate DDR memory controllers are used to drive DDR SDRAM, where data is transferred on the rising and falling access of the memory clock of the system. DDR SDRAM ( double data rate synchronous dynamic random access memory) is a class of memory Integrated circuit used in Computers It achieves nearly twice DDR memory controllers are significantly more complicated than Single Data Rate controllers, but allow for twice the data to be transferred without increasing the clock rate or increasing the bus width to the memory cell.
Dual-channel memory
Dual Channel memory controllers are memory controllers where the DRAM devices are separated on to two different buses to allow two memory controllers to access them in parallel. Dual-channel architecture describes a technology that theoretically doubles data throughput from RAM to the memory controller. This doubles the theoretical amount of bandwidth of the bus. In theory, more channels can be built (a channel for every DRAM cell would be the ideal solution), but due to wire count, line capacitance, and the need for parallel access lines to have identical lengths, more channels are very difficult to add. In Electronics, the term crosstalk ( XT) refers to any phenomenon by which a signal transmitted on one circuit or channel of a Transmission system
Fully buffered memory
Fully buffered memory systems places a memory buffer device on every memory module (called an FB-DIMM when Fully Buffered RAM is used), which unlike traditional memory controller devices, uses a serial data link to the memory controller instead of the parallel link used in previous RAM designs. A DIMM, or dual in-line memory module, comprises a series of Dynamic random access memory Integrated circuits These modules are mounted on a Printed Fully Buffered DIMM (or FB-DIMM is a memory technology which can be used to increase reliability speed and density of memory systems This decreases the number of the wires necessary to place the memory devices on a motherboard (allowing for a smaller number of layers to be used, meaning more memory devices can be placed on a single board), at the expense of increasing latency (the time necessary to access a memory location). This increase is due to the time required to convert the parallel information read from the DRAM cell to the serial format used by the FB-DIMM controller, and back to a parallel form in the memory controller on the motherboard. In theory, the FB-DIMM's memory buffer device could be built to access any DRAM cells, allowing for memory cell agnostic memory controller design, but this has not been demonstrated, as the technology is in its infancy.
See also
External references
- Selecting Memory Controllers for DSP Systems A how-to article on evaluating memory controllers using the VisualSim virtual prototyping tool. Memory scrubbing is the process of detecting and correcting Bit errors in Memory by using error-detecting codes like ECC.
- Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2 A detailed description of the key issues when implementing memory controllers that need to support both DDR2 and DDR3 memories. www. memcoreinc. com.
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