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A MIPS R4400 microprocessor made by Toshiba.
A MIPS R4400 microprocessor made by Toshiba. ( is a multinational conglomerate manufacturing company headquartered in Tokyo, Japan.

MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages) is a RISC microprocessor architecture developed by MIPS Technologies. MIPS Technologies Inc ( formerly MIPS Computer Systems, is most widely known for developing the MIPS architecture and a series of pioneering RISC By the late 1990s it was estimated that one in three RISC chips produced were MIPS-based designs. The Year 2000 problem (also known as the Y2K problem, the millennium bug, the Y2K bug, or simply Y2K) was a notable Computer bug resulting

MIPS designs are currently primarily used in many embedded systems such as the Series2 TiVo, Windows CE devices, Cisco routers, Foneras, and video game consoles like the Nintendo 64 and Sony PlayStation, PlayStation 2, and PlayStation Portable handheld system. An embedded system is a special-purpose Computer system designed to perform one or a few dedicated functions often with Real-time computing constraints TiVo (pronounced ˈtiːvoʊ is a brand of Digital video recorder (DVR in the United States, Canada, and Australia created by TiVo Windows CE (also known officially as Windows Embedded Compact post version 6 A router ('rautər in the USA 'rutər in the UK and Ireland, or either pronunciation in Australia and Canada is a Computer whose software and hardware are usually FON (FON Wireless Ltd is a company that runs a system of shared Wireless networks The business was launched in November 2005 The, often abbreviated as N64, is Nintendo 's third home Video game console for the international market is a multinational conglomerate corporation headquartered in Minato Tokyo, Japan, and one of the world's largest Media conglomerates with The PlayStation (abbreviated PS, PSone, PS1, or informally as PSX) is a 32-bit fifth generation Video game console The PlayStation Portable (officially abbreviated PSP) is a Handheld game console manufactured and marketed by Sony Computer Entertainment. Until late 2006 they were also used in many of SGI's computer products. Silicon Graphics Inc (commonly initialised to SGI, historically sometimes referred to as Silicon Graphics Computer Systems or SGCS) is a company

The early MIPS architectures were 32-bit implementations (generally 32-bit wide registers and data paths), while later versions were 64-bit implementations. Multiple revisions of the MIPS instruction set exist, including MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64. An instruction set is a list of all the instructions and all their variations that a processor can execute The current revisions are MIPS32 (for 32-bit implementations) and MIPS64 (for 64-bit implementations). MIPS32 and MIPS64 define a control register set as well as the instruction set. Several "add-on" extensions are also available, including MIPS-3D which is a simple set of floating-point SIMD instructions dedicated to common 3D tasks, MDMX(MaDMaX) which is a more extensive integer SIMD instruction set using the 64-bit floating-point registers, MIPS16e which adds compression to the instruction stream to make programs take up less room (allegedly a response to the Thumb encoding in the ARM architecture), and the recent addition of MIPS MT, new multithreading additions to the system similar to HyperThreading in the Intel's Pentium 4 processors. In Computing, SIMD ( S ingle I nstruction M ultiple D ata is a technique employed to achieve data level parallelism as in a Vector The MDMX (MIPS Digital Media eXtension also known as MaDMaX is a SIMD computational unit developed for the MIPS family of processors In Computing, SIMD ( S ingle I nstruction M ultiple D ata is a technique employed to achieve data level parallelism as in a Vector The ARM architecture (previously the Advanced RISC Machine, and prior to that Acorn RISC Machine) is a 32-bit RISC processor architecture The ARM architecture (previously the Advanced RISC Machine, and prior to that Acorn RISC Machine) is a 32-bit RISC processor architecture Multithreading computers have hardware support to efficiently execute multiple threads. Hyper-threading (officially termed Hyper-Threading Technology or HTT) is an Intel-proprietary technology

Computer architecture courses in universities and technical schools often study the MIPS architecture. In Computer engineering, computer architecture is the conceptual design and fundamental operational structure of a Computer system The design of the MIPS CPU family greatly influenced later RISC architectures such as DEC Alpha. Alpha, originally known as Alpha AXP, was a 64-bit Reduced instruction set computer (RISC Instruction set architecture (ISA developed

Contents

History

RISC Pioneer

In 1981, a team led by John L. Hennessy at Stanford University started work on what would become the first MIPS processor. Year 1981 ( MCMLXXXI) was a Common year starting on Thursday (link displays the 1981 For other people named John Hennessy see John Hennessy. John LeRoy Hennessy is an American computer scientist and academic Leland Stanford Junior University, commonly known as Stanford University or simply Stanford, is a private Research university located in The basic concept was to dramatically increase performance through the use of deep instruction pipelines, a technique that was well known, but difficult to implement. Pipelining redirects here For HTTP pipelining see HTTP pipelining. Generally in a pipeline architecture, successive instructions in a program sequence will overlap in execution. Modules inside the CPU work in parallel so that the CPU will fetch and start executing an instruction before the preceding instruction is complete. In contrast, traditional designs of the era waited to complete an entire instruction before moving on, thereby leaving large areas of the CPU idle as the process continued.

One major barrier to pipelining was that it required interlocks to be set up to ensure that instructions that took multiple clock cycles to complete would stop the pipeline from loading more data — basically to pause while it completed. These interlocks can take a long time to set up, and were thought to be a major barrier to future speed improvements. A major aspect of the MIPS design was to fit every sub-phase (including memory access) of all instructions into one cycle, thereby removing any needs for interlocking, and permitting a single cycle throughput.

Although this design eliminated a number of useful instructions, notably things like multiply and divide which would take multiple (execution) steps, it was felt that the overall performance of the system would be dramatically improved because the chips could run at much higher clock rates. This ramping of the speed would be difficult with interlocking involved, as the time needed to set up locks is as much a function of die size as clock rate: adding the hardware needed might actually slow down the overall speed.

The elimination of these instructions became a contentious point. Many observers claimed the design (and RISC in general) would never live up to its hype. If one simply replaces the complex multiply instruction with many simpler additions, where is the speed increase? This overly-simple analysis ignored the fact that the speed of the design was in the pipelines, not the instructions.

In 1984 Hennessy was convinced of the future commercial potential of the design, and left Stanford to form MIPS Computer Systems. They released their first design, the R2000, in 1985, improving the design as the R3000 in 1988. These 32-bit CPUs formed the basis of their company through the 1980s, used primarily in SGI's series of workstations. Silicon Graphics Inc (commonly initialised to SGI, historically sometimes referred to as Silicon Graphics Computer Systems or SGCS) is a company A workstation, such as a Unix workstation, RISC workstation or Engineering workstation, is a high-end Microcomputer These commercial designs deviated from the Stanford academic research by implementing most of the interlocks in hardware, supplying full multiply and divide instructions (among others).

In 1991 MIPS released the first 64-bit microprocessor, the R4000. However, MIPS had financial difficulties while bringing it to market. The design was so important to SGI, at the time one of MIPS' few major customers, that SGI bought the company outright in 1992 in order to guarantee the design would not be lost. As a subsidiary of SGI, the company became known as MIPS Technologies. MIPS Technologies Inc ( formerly MIPS Computer Systems, is most widely known for developing the MIPS architecture and a series of pioneering RISC

Licensable Architecture

In the early 1990s MIPS started licensing their designs to third-party vendors. This proved fairly successful due to the simplicity of the core, which allowed it to be used in a number of applications that would have formerly used much less capable CISC designs of similar gate count and price -- the two are strongly related; the price of a CPU is generally related to the number of gates and the number of external pins. A complex instruction set computer ( CISC, pronounced like " sisk " is a Microprocessor Instruction set architecture (ISA in which In Microprocessor design gate count refers to the number of Transistor switches or gates, that are needed to implement a design Sun Microsystems attempted to enjoy similar success by licensing their SPARC core but was not nearly as successful. Sun Microsystems Inc ( is a multinational vendor of Computers computer components Computer software, and Information technology services SPARC (from Scalable Processor Architecture is a RISC Microprocessor Instruction set architecture originally By the late 1990s MIPS was a powerhouse in the embedded processor field, and in 1997 the 48-millionth MIPS-based CPU shipped, making it the first RISC CPU to outship the famous 68k family. An embedded system is a special-purpose Computer system designed to perform one or a few dedicated functions often with Real-time computing constraints The Motorola 680x0 / m68k / 68k / 68K is a family of 32-bit CISC Microprocessor CPU chips and was the primary MIPS was so successful that SGI spun-off MIPS Technologies in 1998. Fully half of MIPS' income today comes from licensing their designs, while much of the rest comes from contract design work on cores that will then be produced by third parties.

In 1999 MIPS formalized their licensing system around two basic designs, the 32-bit MIPS32 (based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V) and the 64-bit MIPS64 (based on MIPS V). NEC, Toshiba and SiByte (later acquired by Broadcom) each obtained licenses for the MIPS64 as soon as it was announced. is a Japanese multinational IT company headquartered in Minato Tokyo, Japan. ( is a multinational conglomerate manufacturing company headquartered in Tokyo, Japan. Broadcom Corporation is an American supplier of Integrated circuits (ICs for broadband communications Broadcom Corporation is an American supplier of Integrated circuits (ICs for broadband communications Philips, LSI Logic and IDT have since joined them. Koninklijke Philips Electronics NV ( Royal Philips Electronics Inc. Success followed success, and today the MIPS cores are one of the most-used "heavyweight" cores in the marketplace for computer-like devices (hand-held computers, set-top boxes, etc. A mobile device (also known as cellphone device, handheld device, handheld computer, "Palmtop" or simply handheld) is a pocket-sized A set-top box (STB or set-top unit (STU is a device that connects to a Television and an external source of signal, turning the signal into ), with other designers fighting it out for other niches. Some indication of their success is the fact that Freescale (spun-off by Motorola) uses MIPS cores in their set-top box designs, instead of their own PowerPC-based cores. Freescale Semiconductor Inc is an American Semiconductor manufacturer Motorola Inc ( is an American, multinational Fortune 100, Telecommunications company based in Schaumburg Illinois. PowerPC is a RISC Instruction set architecture created by the 1991 Apple – IBM – Motorola alliance known as AIM

Since the MIPS architecture is licensable, it has attracted several processor start-up companies over the years. A startup company or start-up is a Company with a limited operating history One of the first start-ups to design MIPS processors was Quantum Effect Devices (see next section). Quantum Effect Devices was a company originally named Quantum Effect Design incorporated in 1991 The MIPS design team that designed the R4300 started the company SandCraft, which designed the R5432 for NEC and later produced the SR71000, one of the first out-of-order execution processors for the embedded market. In Computer engineering, out-of-order execution, OoOE, is a paradigm used in most high-performance Microprocessors to make use of cycles that The original DEC StrongARM team eventually split into two MIPS-based start-ups: SiByte which produced the SB-1250, one of the first high-performance MIPS-based systems-on-a-chip (SOC); while Alchemy Semiconductor (later acquired by AMD) produced the Au-1000 SoC for low-power applications. Digital Equipment Corporation was a pioneering American company in the Computer industry The StrongARM Microprocessor is a faster version of the Advanced RISC Machines ARM design System-on-a-chip or system on chip ( SoC or SOC) refers to integrating all components of a Computer or other electronic System System-on-a-chip or system on chip ( SoC or SOC) refers to integrating all components of a Computer or other electronic System Lexra used a MIPS-like architecture and added DSP extensions for the audio chip market and multithreading support for the networking market. Lexra was a Semiconductor intellectual property core company based in Waltham Massachusetts. Multithreading computers have hardware support to efficiently execute multiple threads. Due to Lexra not licensing the architecture, two lawsuits were started between the two companies. The first was quickly resolved when Lexra promised not to advertise their processors as MIPS-compatible. The second (about MIPS patent 4814976 for handling unaligned memory access) was protracted, hurt both companies' business, and culminated in MIPS Technologies giving Lexra a free license and a large cash payment.

Two companies have emerged that specialize in building Multi-core devices using the MIPS architecture. A multi-core processor (or chip-level multiprocessor, CMP) combines two or more independent cores into a single package composed of a single Integrated Raza Microelectronics Inc purchased the product line from failing Sandcraft and later produced devices that contained 8 CPU cores that were targeted at the telecom and networking markets. RMI Corporation, also known as RMI, formerly known as Raza Microelectronics Inc Cavium Networks, originally a security processor vendor also produced devices with 8 CPU cores for the same markets. Cavium Networks ( is a Mountain View California -based company specializing in ARM -based and MIPS -based network and security processors Both of these companies designed their cores in-house, just licensing the architecture instead of purchasing cores from MIPS.

Losing the Desktop

Among the manufacturers which have made computer workstation systems using MIPS processors are SGI, MIPS Computer Systems, Inc., Whitechapel Workstations, Olivetti, Siemens-Nixdorf, Acer, Digital Equipment Corporation, NEC, and DeskStation. A workstation, such as a Unix workstation, RISC workstation or Engineering workstation, is a high-end Microcomputer Silicon Graphics Inc (commonly initialised to SGI, historically sometimes referred to as Silicon Graphics Computer Systems or SGCS) is a company MIPS Technologies Inc ( formerly MIPS Computer Systems, is most widely known for developing the MIPS architecture and a series of pioneering RISC Whitechapel Computer Works Ltd (WCW was a Computer Workstation company formed in the East End of London, United Kingdom in April 1983 with Ing C Olivetti & Co SpA, known as Olivetti, is an Italian manufacturer of Computers printers and other business machines Siemens Nixdorf Informationssysteme, AG ( SNI) was formed in 1990 by the merger of Nixdorf Computer AG and the Siemens ' Data Information Services Acer Incorporated ( ( is a Taiwanese multinational electronics manufacturer Digital Equipment Corporation was a pioneering American company in the Computer industry is a Japanese multinational IT company headquartered in Minato Tokyo, Japan. DeskStation Technology was a manufacturer of RISC -based computer workstations intended to run Windows NT. Operating systems ported to the architecture include SGI's IRIX, Microsoft's Windows NT (until v4. An operating system (commonly abbreviated OS and O/S) is the software component of a Computer system that is responsible for the management and coordination IRIX is a computer Operating system developed by Silicon Graphics Inc Microsoft Corporation is an American multinational Computer technology Corporation, which rose to dominate the Home computer Windows NT is a family of Operating systems produced by Microsoft, the first version of which was released in July 1993 0), Windows CE, Linux, BSD, UNIX System V, SINIX and MIPS Computer Systems' own RISC/os. Windows CE (also known officially as Windows Embedded Compact post version 6 Linux (commonly pronounced ˈlɪnəks Unix (officially trademarked as UNIX, sometimes also written as Unix with Small caps) is a computer Unix System V, commonly abbreviated SysV (and usually pronounced though rarely written as System 5 was one of the versions of the Unix Operating system Sinix may refer to SINIX, computer operating system Şınıx, Azerbaijan RISC/os was a UNIX Operating system distributed by MIPS Computer Systems Inc

There was speculation in the early 1990s that MIPS, and other powerful RISC processors would overtake the Intel IA32 architecture. IA-32 ( Intel Architecture 32-bit) often generically called X86 or x86-32, is the Instruction set architecture of Intel This was encouraged by the support of the first two versions of Microsoft's Windows NT for DEC Alpha, MIPS and PowerPC - and to a lesser extent the Clipper architecture and SPARC. Microsoft Corporation is an American multinational Computer technology Corporation, which rose to dominate the Home computer Windows NT is a family of Operating systems produced by Microsoft, the first version of which was released in July 1993 Alpha, originally known as Alpha AXP, was a 64-bit Reduced instruction set computer (RISC Instruction set architecture (ISA developed PowerPC is a RISC Instruction set architecture created by the 1991 Apple – IBM – Motorola alliance known as AIM The Clipper architecture is a 32-bit RISC -like Instruction set architecture designed by Fairchild Semiconductor. SPARC (from Scalable Processor Architecture is a RISC Microprocessor Instruction set architecture originally However, as Intel quickly released faster versions of their Pentium class CPUs, Microsoft Windows NT v4. The Pentium brand refers to Intel 's single-core x86 Microprocessor based on the P5 fifth-generation Microarchitecture. Windows NT is a family of Operating systems produced by Microsoft, the first version of which was released in July 1993 0 dropped support for anything but Intel and Alpha. With SGI's decision to transition to the Itanium and IA32 architectures, use of MIPS processors on the desktop has now disappeared almost completely[1]. Itanium is the brand name for 64-bit Intel Microprocessors that implement the Intel Itanium architecture (formerly called IA-64) IA-32 ( Intel Architecture 32-bit) often generically called X86 or x86-32, is the Instruction set architecture of Intel

See main article Advanced Computing Environment. The Advanced Computing Environment ( ACE) was defined by an industry consortium in the early 1990s to be the next generation commodity computing platform the successor to

Embedded markets

Through the 1990s, the MIPS architecture was widely adopted by the embedded market, including for use in computer networking/telecommunications, video arcade games, home video game consoles, computer printers, digital set-top boxes, digital televisions, DSL and cable modems, and personal digital assistants. A computer network is a group of interconnected Computers. Networks may be classified according to a wide variety of characteristics An arcade game is a coin-operated entertainment machine typically installed in businesses such as Restaurants Pubs Video arcades and Family Entertainment A set-top box (STB or set-top unit (STU is a device that connects to a Television and an external source of signal, turning the signal into Digital television (DTV is the sending and receiving of moving images and sound by discrete ( digital) signals in contrast to the analog signals used by ADSL modem or DSL modem is a device used to connect a single Computer or Router to a DSL phone line in order to use an ADSL A cable modem is a type of Modem that provides access to a data signal sent over the Cable television infrastructure

The low power-consumption and heat characteristics of embedded MIPS implementations, the wide availability of embedded development tools, and knowledge about the architecture means use of MIPS microprocessors in embedded roles is likely to remain common.

Synthesizeable Cores for Embedded Markets

In recent years most of the technology used in the various MIPS generations has been offered as IP-cores (building-blocks) for embedded processor designs. In Electronic design a Semiconductor intellectual property core, IP block, IP core, or logic core is a reusable unit of logic cell An embedded system is a special-purpose Computer system designed to perform one or a few dedicated functions often with Real-time computing constraints Both 32-bit and 64-bit basic cores are offered, known as the 4K and 5K respectively, and the design itself can be licensed as MIPS32 and MIPS64. The range of Integer values that can be stored in 32 bits is 0 through 4294967295 or −2147483648 through 2147483647 using Two's complement encoding '64-bit' CPUs have existed in Supercomputers since the 1960s and in RISC -based workstations and servers since the early 1990s. These cores can be mixed with add-in units such as FPUs, SIMD systems, various input/output devices, etc. In Computing, SIMD ( S ingle I nstruction M ultiple D ata is a technique employed to achieve data level parallelism as in a Vector

MIPS cores have been commercially successful, now being used in many consumer and industrial applications. MIPS cores can be found in newer Cisco, Linksys and Mikrotik's routerboard routers, cable modems and ADSL modems, smartcards, laser printer engines, set-top boxes, robots, handheld computers, Sony PlayStation 2 and Sony PlayStation Portable. Linksys, founded in 1988 and acquired by Cisco Systems in 2003, is the leader in sales of home and small office network products Mikrotīkls Ltd, known internationally as MikroTik, is a Latvian manufacturer of Computer networking equipment A cable modem is a type of Modem that provides access to a data signal sent over the Cable television infrastructure Asymmetric Digital Subscriber Line ( ADSL) is a form of DSL, a data communications technology that enables faster data transmission over Copper Telephone A smart card, chip card, or Integrated circuit card ( ICC) is any pocket-sized card with embedded integrated A laser printer is a common type of Computer printer that rapidly produces high quality text and graphics on plain paper A set-top box (STB or set-top unit (STU is a device that connects to a Television and an external source of signal, turning the signal into A robot is a mechanical or Virtual Artificial agent In practice it is usually an electro-mechanical system which by its appearance or movements The PlayStation Portable (officially abbreviated PSP) is a Handheld game console manufactured and marketed by Sony Computer Entertainment. In cellphone/PDA applications, the MIPS core has been unable to displace the incumbent, competing ARM core. The ARM architecture (previously the Advanced RISC Machine, and prior to that Acorn RISC Machine) is a 32-bit RISC processor architecture

Examples of MIPS-powered devices: Broadcom BCM5352E - WiFi router processor with 54g WLAN, fast Ethernet, 200 MHz, 16KB ins. Broadcom Corporation is an American supplier of Integrated circuits (ICs for broadband communications Wi-Fi (ˈwaɪfaɪ is the trade name for the popular wireless technology used 8KB data cache, 256B prefetch cache, MMU, 16-bit 100 MHz SDRAM controller, serial/parallel flash, 5-port 100 Mbit/s Ethernet (switch), 16 GPIO, JTAG, 2xUART, 336-ball BGA. BCM 11xx, 12xx, 14xx - 64bit "SiByte" MIPS line.

MIPS architecture processors include: IDT RC32438; ATI Xilleon; Alchemy Au1000, 1100, 1200; Broadcom Sentry5; RMI XLR7xx, Cavium Octeon CN30xx, CN31xx and CN38xx; Infineon Technologies EasyPort, Amazon, Danube, ADM5120, WildPass, INCA-IP, INCA-IP2; NEC EMMA and EMMA2, NEC VR4181A, VR4121, VR4122, VR4181A, VR5432, VR5500; Oak Technologies Generation; PMC-Sierra RM11200; QuickLogic QuickMIPS ESP; Toshiba "Donau", Toshiba TMPR492x, TX4925, TX9956, TX7901. Cavium Networks ( is a Mountain View California -based company specializing in ARM -based and MIPS -based network and security processors Infineon Technologies AG () was founded in April 1999 when the Semiconductor operations of parent company Siemens AG, were spun off to form a separate is a Japanese multinational IT company headquartered in Minato Tokyo, Japan. Oak Technology was a supplier of Semiconductor chips for sound cards graphics cards and optical storage devices such as CD-ROM, CD-RW and DVD For the former computer game manufacturer see Sierra Entertainment. QuickLogic Corporation ( is a manufacturer of Programmable logic devices Until recently they were a supplier of Field-Programmable Gate Arrays based on ( is a multinational conglomerate manufacturing company headquartered in Tokyo, Japan.

MIPS based Supercomputers

One of the more interesting applications of the MIPS architecture is its use in massive processor count supercomputers. Silicon Graphics (SGI) refocused its business from desktop graphics workstations to the high performance computing (HPC) market in the early 1990s. Silicon Graphics Inc (commonly initialised to SGI, historically sometimes referred to as Silicon Graphics Computer Systems or SGCS) is a company The success of the company's first foray into server systems, the Challenge series based on the R4400 and R8000, and later R10000, motivated SGI to create a vastly more powerful system. The Challenge, code named Eveready (deskside models and Terminator (rackmount models is a family of server computers and Supercomputers developed The introduction of the integrated R10000 allowed SGI to produce a system, the Origin 2000, eventually scalable to 1024 CPUs using its NUMAlink cc-NUMA interconnect. The SGI Origin 2000, code named Lego, is a family of mid-range and high-end servers developed and manufactured by SGI, introduced in 1996 to succeed the NUMAlink is a system interconnect developed by SGI for use in its Distributed shared memory CcNUMA computer systems The Origin 2000 begat the Origin 3000 series which topped out with the same 1024 maximum CPU count but using the R14000 and R16000 chips up to 700 MHz. The Origin 3000 and the Onyx 3000 is a family of mid-range and high-end computers developed and manufactured by SGI. Its MIPS based supercomputers were withdrawn in 2005 when SGI made the strategic decision to move to Intel's IA-64 architecture.

An HPC startup introduced a radical MIPS based supercomputer in 2007. SiCortex, Inc. has created a tightly integrated Linux cluster supercomputer based on the MIPS64 architecture and a high performance interconnect based on the Kautz digraph topology. Linux (commonly pronounced ˈlɪnəks The system is very power efficient and computationally powerful. The most unique aspect of the system is its multicore processing node which integrates six MIPS64 cores, a crossbar memory controller, interconnect DMA engine, Gigabit Ethernet and PCI Express controllers all on a single chip which consumes only 10 watts of power, yet has a peak floating point performance of 6 GFLOPs. The memory controller is a chip on a computer's Motherboard or CPU die which manages the flow of data going to and from the memory. The most powerful configuration, the SC5832, is a single cabinet supercomputer consisting of 972 such node chips for a total of 5832 MIPS64 processor cores and 5. 8 teraFLOPS of peak performance.

CPU family

Pipeline MIPS
Pipeline MIPS

The first commercial MIPS CPU model, the R2000, was announced in 1985. Year 1985 ( MCMLXXXV) was a Common year starting on Tuesday (link displays 1985 Gregorian calendar) It added multiple-cycle multiply and divide instructions in a somewhat independent on-chip unit. New instructions were added to retrieve the results from this unit back to the execution core; these result-retrieving instructions were interlocked.

The R2000 could be booted either big-endian or little-endian. It had thirty-two 32-bit general purpose registers, but no condition code register (the designers considered it a potential bottleneck), a feature it shares with the AMD 29000 and the DEC Alpha. A status register (also flag register or condition code register (CCR) is a collection of flag Bits for a processor. AMD 29000, often simply 29k, was a popular family of RISC -based 32-bit Microprocessors and Microcontrollers from Advanced Micro Devices Alpha, originally known as Alpha AXP, was a 64-bit Reduced instruction set computer (RISC Instruction set architecture (ISA developed Unlike other registers the program counter is not directly accessible. The program counter, or shorter PC (also called the instruction pointer, part of the instruction sequencer in some Computers is a register in

The R2000 also had support for up to four co-processors, one of which was built into the main CPU and handled exceptions, traps and memory management, while the other three were left for other uses. One of these could be filled by the optional R2010 FPU, which had thirty-two 32-bit registers that could be used as sixteen 64-bit registers for double-precision. A floating point unit (FPU is a part of a Computer system specially designed to carry out operations on Floating point numbers

The R3000 succeeded the R2000 in 1988, adding 32 kB (soon increased to 64 KB) caches for instructions and data, along with cache coherency support for multi-processor use. Year 1988 ( MCMLXXXVIII) was a Leap year starting on Friday (link displays 1988 Gregorian calendar) In computing Cache coherency (also cache coherence) refers to the integrity of data stored in local caches of a shared resource While there were flaws in the R3000's multiprocessor support, it still managed to be a part of several successful multiprocessor designs. The R3000 also included a built-in MMU, a common feature on CPUs of the era. A memory management unit ( MMU) sometimes called paged memory management unit ( PMMU) is a Computer hardware component responsible for handling The R3000 was the first successful MIPS design in the marketplace, and eventually over 1 million were made. The R3000A, used in the extremely successful Sony PlayStation, was a speed bumped version running at 40 MHz that delivered a performance of 32 VUPs. is a multinational conglomerate corporation headquartered in Minato Tokyo, Japan, and one of the world's largest Media conglomerates with The PlayStation (abbreviated PS, PSone, PS1, or informally as PSX) is a 32-bit fifth generation Video game console Instructions per second (IPS is a measure of a Computer 's processor speed Like the R2000, the R3000 was paired with the R3010 FPU. Pacemips produced an R3400 and IDT produced R3500, both of them were R3000s with R3010 fpu on a single chip. IDT ( was founded in 1980 as a Semiconductor vendor Employing approximately 2500 people worldwide headquartered in San Jose California and operating Toshiba's R3900 was a virtually first SoC for the early Handheld PCs based on the Windows CE. ( is a multinational conglomerate manufacturing company headquartered in Tokyo, Japan. System-on-a-chip or system on chip ( SoC or SOC) refers to integrating all components of a Computer or other electronic System Handheld PC, or H/PC for short is a term for a Computer built around a form factor which is smaller than any standard Laptop computer. Windows CE (also known officially as Windows Embedded Compact post version 6 The Mongoose-V is a radiation-hardened and expanded version of the MIPS R3000 CPU paired with an on-chip R3010 FPU used for space applications. The Mongoose-V 32-bit Microprocessor for Spacecraft on-board computer applications is a radiation-hardened and expanded 10&ndash15 MHz

The R4000 series, released in 1991, extended the MIPS instruction set to a full 64-bit architecture, moved the FPU onto the main die to create a single-chip mic, and operated at a radically high internal clock speed (it was introduced at 100 MHz). However, in order to achieve the clock speed the caches were reduced to 8 KB each and took three cycles to access. The high operating frequencies were achieved through the technique of deep pipelining (called super-pipelining at the time). Pipelining redirects here For HTTP pipelining see HTTP pipelining. With the introduction of the R4000 a number of improved versions soon followed, including the R4400 of 1993 which included 16 KB caches, largely bug-free 64-bit operation, and support for a larger external level 2 cache.

MIPS, now a division of SGI called MTI, designed the lower-cost R4200, and later the even lower cost R4300, which was the R4200 with a 32-bit external bus. The Nintendo 64 used a NEC VR4300 CPU that was based upon the low-cost MIPS R4300i. The, often abbreviated as N64, is Nintendo 's third home Video game console for the international market is a Japanese multinational IT company headquartered in Minato Tokyo, Japan. [2]

bottom-side view of package of R4700 Orion with the exposed silicon chip, fabricated by IDT, designed by Quantum Effect Devices
bottom-side view of package of R4700 Orion with the exposed silicon chip, fabricated by IDT, designed by Quantum Effect Devices
topside view of package for R4700 Orion
topside view of package for R4700 Orion

Quantum Effect Devices (QED), a separate company started by refugees from MIPS, designed the R4600 "Orion", the R4700 "Orion", the R4650 and the R5000. IDT ( was founded in 1980 as a Semiconductor vendor Employing approximately 2500 people worldwide headquartered in San Jose California and operating Quantum Effect Devices was a company originally named Quantum Effect Design incorporated in 1991 Quantum Effect Devices was a company originally named Quantum Effect Design incorporated in 1991 Where the R4000 had pushed clock frequency and sacrificed cache capacity, the QED designs emphasized large caches which could be accessed in just two cycles and efficient use of silicon area. The R4600 and R4700 were used in low-cost versions of the SGI Indy workstation as well as the first MIPS based Cisco routers, such as the 36x0 and 7x00-series routers. Introduced in 1993 the Indy, code named Guinness, was the fruit of SGI 's effort to muscle into the market for desktop publishing low-end CAD, and The R4650 was used in the original WebTV set-top boxes (now Microsoft TV). MSN TV (formerly WebTV) is the name of both a Thin client which uses a Television for display (rather than a Computer monitor) and the The R5000 FPU had more flexible single precision floating-point scheduling than the R4000, and as a result, R5000-based SGI Indys had much better graphics performance than similarly clocked R4400 Indys with the same graphics hardware. SGI gave the old graphics board a new name when it was combined with R5000 in order to emphasize the improvement. QED later designed the RM7000 and RM9000 family of devices for embedded markets like networking and laser printers. QED was acquired by the semiconductor manufacturer PMC-Sierra in August 2000, the latter company continuing to invest in the MIPS architecture. For the former computer game manufacturer see Sierra Entertainment. August 2000: January - February - March - April - May - June - July - August - September The RM7000 included an on-board 256 kB level 2 cache and a controller for optional level three cache. The RM9xx0 were a family of SOC devices which included northbridge peripherals such as memory controller, PCI controller, gigabit ethernet controller and fast IO such as a hypertransport port. System-on-a-chip or system on chip ( SoC or SOC) refers to integrating all components of a Computer or other electronic System The northbridge, also known as the memory controller hub ( MCH) in Intel systems (AMD VIA SiS and others usually use 'northbridge' is traditionally one The memory controller is a chip on a computer's Motherboard or CPU die which manages the flow of data going to and from the memory. The Peripheral Component Interconnect, or PCI Standard (commonly PCI) specifies a Computer bus for attaching peripheral devices to a Computer Gigabit Ethernet (GbE or 1 GigE is a term describing various technologies for transmitting Ethernet frames at a rate of a gigabit per second, as defined by the

The R8000 (1994) was the first superscalar MIPS design, able to execute two integer or floating point and two memory instructions per cycle. Year 1994 ( MCMXCIV) was a Common year starting on Saturday (link will display full 1994 Gregorian calendar) A superscalar CPU architecture implements a form of parallelism called Instruction-level parallelism within a single processor The design was spread over six chips: an integer unit (with 16 KB instruction and 16 KB L1 data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4 MB off-chip secondary cache. The R8000 powered SGI's POWER CHALLENGE servers in the mid 1990s and later became available in the POWER Indigo2 workstation. The Challenge, code named Eveready (deskside models and Terminator (rackmount models is a family of server computers and Supercomputers developed Although its FPU performance fit scientific users quite well, its limited integer performance and high cost dampened appeal for most users, and the R8000 was in the marketplace for only a year and remains fairly rare.

In 1995, the R10000 was released. Year 1995 ( MCMXCV) was a Common year starting on Sunday. Events of 1995 This processor was a single-chip design, ran at a faster clock speed than the R8000, and had larger 32 KB primary instruction and data caches. It was also superscalar, but its major innovation was out-of-order execution. Even with a single memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density made the R10000 preferable for most customers.

Recent designs have all been based upon R10000 core. The R12000 used improved manufacturing to shrink the chip and operate at higher clock rates. The revised R14000 allowed higher clock rates with additional support for DDR SRAM in the off-chip cache, and a faster front side bus clocked to 200 MHz for better throughput. DDR SDRAM ( double data rate synchronous dynamic random access memory) is a class of memory Integrated circuit used in Computers It achieves nearly twice Static random access memory (SRAM is a type of Semiconductor memory where the word static indicates that unlike ''dynamic'' RAM (DRAM, it does not In Personal computers the Front Side Bus ( FSB) is the bus that carries data between the CPU and the northbridge. Later iterations are named the R16000 and the R16000A and feature increased clock speed, additional L1 cache, and smaller die manufacturing compared with before.

Other members of the MIPS family include the R6000, an ECL implementation of the MIPS architecture which was produced by Bipolar Integrated Technology. Bipolar Integrated Technology was a Semiconductor company based in Beaverton Oregon which sold products implemented with ECL technology The R6000 microprocessor introduced the MIPS II instruction set. Its TLB and cache architecture are different from all other members of the MIPS family. A Translation lookaside buffer ( TLB) is a CPU cache that is used by memory management hardware to improve the speed of Virtual address The R6000 did not deliver the promised performance benefits, and although it saw some use in Control Data machines, it quickly disappeared from the mainstream market. Control Data Corporation (CDC, was one of the pioneering Supercomputer firms

MIPS Microprocessors
Model Frequency (MHz) Year Process (µm) Transistors (Millions) Die Size (mm²) Pin Count Power (W) Voltage Dcache (KB) Icache (KB) L2 Cache L3 Cache
R2000 8-16. 7 1985 2. 0 0. 11 ? ? ? ? 32 64 None None
R3000 12-40 1988 1. 2 0. 11 66. 12 145 4 ? 64 64 0-256 KB External None
R4000 100 1991 0. 8 1. 35 213 179 15 5 8 8 1 MB External None
R4400 100-250 1992 0. 6 2. 3 186 179 15 5 16 16 1-4 MB External None
R4600 100-133 1994 0. 64 2. 2 77 179 4. 6 5 16 16 512 KB External None
R5000 150-200 1996 0. 35 3. 7 84 223 10 3. 3 32 32 1 MB External None
R8000 75-90 1994 0. 7 2. 6 299 591+591 30 3. 3 16 16 4 MB External None
R10000 150-250 1996 0. 35, 0. 25 6. 7 299 599 30 3. 3 32 32 1-4 MB External None
R12000 270-400 1998 0. 25, 0. 18 6. 9 204 600 20 4 32 32 2 MB External None
RM7000 250-600 1998 0. 25, 0. 18, 0. 13 18 91 304 10, 6, 3 3. 3, 2. 5, 1. 5 16 16 256 KB Internal 1 MB External
R14000 500-600 2001 0. 13 7. 2 204 527 17 ? 32 32 2-4 MB External None
R16000 700-1000 2002 0. 11 ? ? ? 20 ? 64 64 4-16 MB External None

Note: These specifications are for common processor models. Variations exist, especially in Level 2 cache.

Note: The R8000 has a unique cache hierarchy named 'Data Streaming Cache' where there is 16 KB of L1 data cache for the integer chip with an external 4 MB L2 cache that served as the secondary unified cache for the integer chip but the as the L1 data cache for the floating point chip.

Summary of R3000 instruction set Opcodes

Instructions are divided into three types: R, I and J. Every instruction starts with a 6-bit opcode. In addition to the opcode, R-type instructions specify three registers, a shift amount field, and a function field; I-type instructions specify two registers and a 16-bit immediate value; J-type instructions follow the opcode with a 26-bit jump target. [3][4]

The following are the three formats used for the core instruction set:

Type -31-                                 format (bits)                                 -0-
R opcode (6) rs (5) rt (5) rd (5) shamt (5) funct (6)
I opcode (6) rs (5) rt (5) immediate (16)
J opcode (6) address (26)

MIPS Assembly Language

These are assembly language instructions that have direct hardware implementation, as opposed to pseudoinstructions which are translated into multiple real instructions before being assembled.

Category Name Instruction syntax Meaning Format/opcode/funct Notes
Arithmetic Add add $1,$2,$3 $1 = $2 + $3 (signed) R 0 2016 adds two registers, extends sign to width of register
Add unsigned addu $1,$2,$3 $1 = $2 + $3 (unsigned) R 0 2116 as above without sign extension
Subtract sub $1,$2,$3 $1 = $2 - $3 (signed) R 0 2216 subtracts two registers
Subtract unsigned subu $1,$2,$3 $1 = $2 - $3 (unsigned) R 0 as above without sign extension
Add immediate addi $1,$2,CONST $1 = $2 + CONST (signed) I 816 Used to add constants (and also to copy one register to another "addi $1, $2, 0"), with sign extension
Add immediate unsigned addiu $1,$2,CONST $1 = $2 + CONST (unsigned) I 916 as above without sign extension
Multiply mult $1,$2 LO = (($1 * $2) << 32) >> 32;
HI = ($1 * $2) >> 32;		 R 0 1816 Multiplies two registers and puts the 64-bit result in two special memory spots - LOW and HI. Alternatively, one could say the result of this operation is: (int HI,int LO) = (64-bit) $1 * $2 . See mfhi and mflo for accessing LO and HI regs.
Divide div $1, $2 LO = $1 / $2     HI = $1 % $2 R Divides two registers and puts the 32-bit integer result in LO and the remainder in HI. [3]
Data Transfer Load double word ld $1,CONST($2) $1 = Memory[$2 + CONST] I 2316 loads the word stored from: MEM[$2+CONST] and the following 7 bytes to $1 and the next register.
Load word lw $1,CONST($2) $1 = Memory[$2 + CONST] I 2316 loads the word stored from: MEM[$2+CONST] and the following 3 bytes.
Load halfword lh $1,CONST($2) $1 = Memory[$2 + CONST] (signed) I 2516 loads the halfword stored from: MEM[$2+CONST] and the following byte. Sign is extended to width of register.
Load halfword unsigned lhu $1,CONST($2) $1 = Memory[$2 + CONST] (unsigned) I As above without sign extension.
Load byte lb $1,CONST($2) $1 = Memory[$2 + CONST] (signed) I loads the byte stored from: MEM[$2+CONST].
Load byte unsigned lbu $1,CONST($2) $1 = Memory[$2 + CONST] (unsigned) I As above without sign extension.
Store double word sd $1,CONST($2) Memory[$2 + CONST] = $1 I stores two words from $1 and the next register into: MEM[$2+CONST] and the following 7 bytes. The order of the operands is a large source of confusion.
Store word sw $1,CONST($2) Memory[$2 + CONST] = $1 I stores a word into: MEM[$2+CONST] and the following 3 bytes. The order of the operands is a large source of confusion.
Store half sh $1,CONST($2) Memory[$2 + CONST] = $1 I stores the first half of a register (a halfword) into: MEM[$2+CONST] and the following byte.
Store byte sb $1,CONST($2) Memory[$2 + CONST] = $1 I stores the first fourth of a register (a byte) into: MEM[$2+CONST].
Load upper immediate lui $1,CONST $1 = CONST << 16 I loads a 16-bit immediate operand into the upper 16-bits of the register specified. Maximum value of constant is 216-1
Move from high mfhi $1 $1 = HI R Moves a value from HI to a register. Do not use a multiply or a divide instruction within two instructions of mfhi (that action is undefined because of the MIPS pipeline).
Move from low mflo $1 $1 = LO R 0 1216 Moves a value from LO to a register. Do not use a multiply or a divide instruction within two instructions of mflo (that action is undefined because of the MIPS pipeline).
Move from Control Register mfcZ $1, $2 $1 = Coprocessor[Z]. ControlRegister[$2] R Moves a 4 byte value from Coprocessor Z Control register to a general purpose register. Sign extension.
Move to Control Register mtcZ $1, $2 Coprocessor[Z]. ControlRegister[$2] = $1 R Moves a 4 byte value from a general purpose register to a Coprocessor Z Control register. Sign extension.
Load word coprocessor lwcZ $1,CONST ($2) Coprocessor[Z]. DataRegister[$1] = Memory[$2 + CONST] I Loads the 4 byte word stored from: MEM[$2+CONST] into a Coprocessor data register. Sign extension.
Store word coprocessor swcZ $1,CONST ($2) Memory[$2 + CONST] = Coprocessor[Z]. DataRegister[$1] I Stores the 4 byte word held by a Coprocessor data register into: MEM[$2+CONST]. Sign extension.
Logical And and $1,$2,$3 $1 = $2 & $3 R Bitwise and
And immediate andi $1,$2,CONST $1 = $2 & CONST I
Or or $1,$2,$3 $1 = $2 | $3 R Bitwise or
Or immediate ori $1,$2,CONST $1 = $2 | CONST I
Exclusive or xor $1,$2,$3 $1 = $2 ^ $3 R
Nor nor $1,$2,$3 $1 = ~ ($2 | $3) R Bitwise nor
Set on less than slt $1,$2,$3 $1 = ($2 < $3) R Tests if one register is less than another.
Set on less than immediate slti $1,$2,CONST $1 = ($2 < CONST) I Tests if one register is less than a constant.
Bitwise Shift Shift left logical sll $1,$2,CONST $1 = $2 << CONST R shifts CONST number of bits to the left (multiplies by 2CONST)
Shift right logical srl $1,$2,CONST $1 = $2 >> CONST R shifts CONST number of bits to the right - zeros are shifted in (divides by 2CONST). Note that this instruction only works as division of a two's complement number if the value is positive.
Shift right arithmetic sra $1,$2,CONST $1 = $2 >> CONST + \
\bigg(\bigg(\sum_{n=1}^{CONST}2^{31-n}\bigg)\cdot $2 >> 31 \bigg) 		R shifts CONST number of bits - the sign bit is shifted in (divides 2's complement number by 2CONST)
Conditional branch Branch on equal beq $1,$2,CONST if ($1 == $2) go to PC+4*CONST I Goes to the instruction at the specified address if two registers are equal. The two's complement of a Binary number is defined as the value obtained by subtracting the number from a large power of two (specifically from 2 N for
Branch on not equal bne $1,$2,CONST if ($1 != $2) go to PC+4*CONST I Goes to the instruction at the specified address if two registers are not equal.
Unconditional jump Jump j CONST goto address CONST J Unconditionally jumps to the instruction at the specified address.
Jump register jr $1 goto address $1 R Jumps to the address contained in the specified register
Jump and link jal CONST $31 = PC + 4; goto CONST J For procedure call - used to call a subroutine, $31 holds the return address; returning from a subroutine is done by: jr $31

NOTE: in the branching and jump instructions, the offset can be replaced by a label present somewhere in the code.

NOTE: that there is no corresponding "load lower immediate" instruction; this can be done by using addi (add immediate, see below) or ori (or immediate) with the register $0 (whose value is always zero). For example, both addi $1, $0, 100 and ori $1, $0, 100 load the decimal value 100 into register $1.

NOTE: An arithmetic operation with signed immediates differs from one with unsigned ones in that it does not throw an exception. Subtracting an immediate can be done with adding the negation of that value as the immediate.

Pseudo instructions

These instructions are accepted by the MIPS assembler, however they are not real instructions within the MIPS instruction set. Instead, the assembler translates them into sequences of real instructions.

Name instruction syntax Real instruction translation meaning
Load Address la $1, LabelAddr lui $1, LabelAddr[31:16]; ori $1,$1, LabelAddr[15:0] $1 = Label Address
Load Immediate li $1, IMMED[31:0] lui $1, IMMED[31:16]; ori $1,$1, IMMED[15:0] $1 = 32 bit Immediate value
Branch if greater than bgt if(R[rs]>R[rt]) PC=Label
Branch if less than blt if(R[rs]<R[rt]) PC=Label
Branch if greater than or equal bge if(R[rs]>=R[rt]) PC=Label
branch if less than or equal ble if(R[rs]<=R[rt]) PC=Label
branch if greater than unsigned bgtu if(R[rs]=>R[rt]) PC=Label
branch if greater than zero bgtz if(R[rs]>0) PC=Label

Some other important instructions

Compiler Register Usage

Main article: calling convention#MIPS

The hardware architecture specifies that:

These are the only hardware restrictions on the usage of the general purpose registers.

The various MIPS tool-chains implement specific calling conventions that further restrict how the registers are used. These calling conventions are totally maintained by the tool-chain software and are not required by the hardware. In Computer science, a calling convention is a standardized method for a program to pass parameters to a function and receive a result value back from it

Registers
Name Number Use Callee must preserve?
$zero $0 constant 0 N/A
$at $1 assembler temporary no
$v0–$v1 $2–$3 Values for function returns and expression evaluation no
$a0–$a3 $4–$7 function arguments no
$t0–$t7 $8–$15 temporaries no
$s0–$s7 $16–$23 saved temporaries yes
$t8–$t9 $24–$25 temporaries no
$k0–$k1 $26–$27 reserved for OS kernel no
$gp $28 global pointer yes
$sp $29 stack pointer yes
$fp $30 frame pointer yes
$ra $31 return address N/A

Registers that are preserved across a call are registers that (by convention) will not be changed by a system call or procedure (function) call. Stacks in computing architectures are regions of memory where data is added or removed in a Last-In-First-Out manner In Computer science, a call stack is a dynamic stack data structure which stores information about the active Subroutines of a Computer program In postal Mail, a return address is an explicit inclusion of the address of the person sending the message For example, $s-registers must be saved to the stack by a procedure that needs to use them, and $sp and $fp are always incremented by constants, and decremented back after the procedure is done with them (and the memory they point to). By contrast, $ra is changed automatically by any normal function call (ones that use jal), and $t-registers must be saved by the program before any procedure call (if the program needs the values inside them after the call).

Simulators

There is a freely available "MIPS32 Simulator" (earlier versions simulated only the R2000/R3000) called SPIM for several operating systems (specifically Unix or GNU/Linux; Mac OS X; MS Windows 95, 98, NT, 2000, XP; and DOS) which is good for learning MIPS assembly language programming and the general concepts of RISC-assembly language programming: http://www.cs.wisc.edu/~larus/spim.html

EduMIPS64 is a GPL graphical cross-platform MIPS64 CPU simulator, written in Java/Swing. SPIM is a MIPS processor simulator designed to run Assembly language code for this architecture It supports a wide subset of the MIPS64 ISA and allows the user to graphically see what happens in the pipeline when an assembly program is run by the CPU. It has educational purposes and is used in some Computer Architecture courses in Universities around the world. More info at http://www.edumips.org

MARS is another GUI based MIPS emulator designed for use in education, specifically for use with Hennessy's Computer Organization and Design. More information is available at http://courses.missouristate.edu/KenVollmar/MARS/

More advanced free MIPS emulators are available from the GXemul (formerly known as the mips64emul project) and QEMU projects, which emulate not only the various MIPS III and higher microprocessors (from the R4000 through the R10000), but also entire computer systems which use the microprocessors. GXemul (formerly known as mips64emul) is a Computer architecture Emulator being developed by Anders Gavare QEMU is a processor Emulator that relies on dynamic Binary translation to achieve a reasonable speed while being easy to port on new host CPU architectures For example, GXemul can emulate both a DECstation with a MIPS R4400 CPU (and boot to Ultrix), and an SGI O2 with a MIPS R10000 CPU (although the ability to boot Irix is limited), among others, as well as the various framebuffers, SCSI controllers, and the like which comprise those systems. The DECstation was a brand of computers used by DEC, and refers to three distinct lines of computer systems&mdashthe first released in 1978 as a Word processing Ultrix (officially all-caps ULTRIX) was the brand name of Digital Equipment Corporation 's (DEC native Unix systems The O2 is an entry-level Unix Workstation introduced in 1996 by Silicon Graphics (SGI to replace their earlier Indy series IRIX is a computer Operating system developed by Silicon Graphics Inc A framebuffer is a video output device that drives a video display from a memory buffer containing a complete frame of data

Commercial simulators are available especially for the embedded use of MIPS processors, for example Virtutech Simics (MIPS 4Kc and 5Kc, PMC RM9000, QED RM7000), VaST Systems (R3000, R4000), and CoWare (the MIPS4KE, MIPS24K, MIPS25Kf and MIPS34K). Simics is a full-system simulator used to run unchanged production binaries of the target hardware at high-performance speeds CoWare is a supplier of platform-driven Electronic system level (ESL design software and services

Examples of system calls (used by SPIM)
service Trap code Input Output Notes
print_int $v0 = 1 $a0 = integer to print prints $a0 to standard output
print_float $v0 = 2 $f12 = float to print prints $f12 to standard output
print_double $v0 = 3 $f12 = double to print prints $f12 to standard output
print_string $v0 = 4 $a0 = address of first character prints a character string to standard output
read_int $v0 = 5 integer read from standard input placed in $v0
read_float $v0 = 6 float read from standard input placed in $f0
read_double $v0 = 7 double read from standard input placed in $f0
read_string $v0 = 8 $a0 = address to place string, $a1 = max string length reads standard input into address in $a0
sbrk $v0 = 9 $a0 = number of bytes required $v0= address of allocated memory Allocates memory from the heap
exit $v0 = 10
print_char $v0 = 11 $a0 = character (low 8 bits)
read_char $v0 = 12 $v0 = character (no line feed) echoed
file_open $v0 = 13 $a0 = full path (zero terminated string with no line feed), $a1 = flags, $a2 = UNIX octal file mode (0644 for rw-r--r--) $v0 = file descriptor
file_read $v0 = 14 $a0 = file descriptor, $a1 = buffer address, $a2 = amount to read in bytes $v0 = amount of data in buffer from file (-1 = error, 0 = end of file)
file_write $v0 = 15 $a0 = file descriptor, $a1 = buffer address, $a2 = amount to write in bytes $v0 = amount of data in buffer to file (-1 = error, 0 = end of file)
file_close $v0 = 16 $a0 = file descriptor

Flags:

Read = 0x0, Write = 0x1, Read/Write = 0x2

OR Create = 0x100, Truncate = 0x200, Append = 0x8

OR Text = 0x4000, Binary = 0x8000

Trivia

Notes

  1. ^ SGI announcing the end of MIPS
  2. ^ NEC Offers Two High Cost Performance 64-bit RISC Microprocessors
  3. ^ a b MIPS R3000 Instruction Set Summary
  4. ^ MIPS Instruction Reference

Further reading

See also

External links

The DLX is a RISC processor architecture design by John L Hennessy and David A For other people named John Hennessy see John Hennessy. John LeRoy Hennessy is an American computer scientist and academic Loongson (龙芯 academic name Godson, also known as Dragon chip) is a family of general-purpose CPUs developed at ICT (Institute of Computing MIPS-X is a Microprocessor and Instruction set architecture developed as a follow-on project to the MIPS architecture at Stanford University The Mongoose-V 32-bit Microprocessor for Spacecraft on-board computer applications is a radiation-hardened and expanded 10&ndash15 MHz
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