Centaur Technology is an x86 CPU design company, now a wholly owned subsidiary of VIA Technologies, a member of the Formosa Plastics Group, Taiwan's largest industrial conglomerate. See also X86 assembly language The generic term x86 refers to the most commercially successful Instruction set architecture in the history of Personal VIA Technologies ( is a Taiwanese manufacturer of Integrated circuits mainly Motherboard Chipsets CPUs, and memory, and Formosa Plastics Group ( Ch: 台塑關係企業 is a Taiwanese conglomerate of diverse interests including Biotechnology, Petrochemical processing Taiwan ( Taiwanese: Tâi-oân/Tāi-oân (historically 大灣/台員/大員/台圓/大圓/台窩灣 is an Island in East Asia.

Contents 1 History 2 Design methodology 2.1 VIA C3 2.2 VIA C7 2.3 Comparative die size 3 References 4 External links

History

Centaur Technologies Inc. was founded in April 1995 by Glenn Henry, Terry Parks, Darius Gaskins, and Al Sato. The funding came from Integrated Device Technology, Inc (IDT). IDT ( was founded in 1980 as a Semiconductor vendor Employing approximately 2500 people worldwide headquartered in San Jose California and operating The business goal was to develop compatible x86 processors that were much less expensive than Intel processors and consumed much less power. See also X86 assembly language The generic term x86 refers to the most commercially successful Instruction set architecture in the history of Personal

There were two fundamental elements of the plan. First, a unique design, developed from scratch, of an x86 processor core optimized differently than Intel's cores. Second, a unique management approach designed to achieve high productivity.

While founded by IDT, three different Centaur designs were shipped under the marketing name of WinChip. The WinChip series was a low-power Socket 7 -based X86 processor designed by Centaur Technology and marketed by its parent company In September 1999, Centaur was purchased from IDT by VIA Technologies, a Taiwanese company. VIA Technologies ( is a Taiwanese manufacturer of Integrated circuits mainly Motherboard Chipsets CPUs, and memory, and Since then, five designs have shipped with marketing name of VIA C3, and the latest design, now shipping as the VIA C7 processor. The VIA C3 is a family of X86 Central processing units for Personal computers designed by Centaur Technology and sold by VIA Technologies The VIA C7 is an X86 Central processing unit designed by Centaur Technology and sold by VIA Technologies.

Design methodology

While slower than x86 CPUs being sold by AMD and Intel, both in absolute terms and on a clock for clock basis, Centaur's chips are much smaller, cheaper to manufacture and consume less power. This makes them highly attractive in the embedded marketplace, and increasingly in the mobile sector as well. An embedded system is a special-purpose Computer system designed to perform one or a few dedicated functions often with Real-time computing constraints

There is a significant performance gap that exists between Centaur and competing x86 chips. Centaur design philosophy was always centered around "sufficient" performance for tasks, that its target market demands. Some of the design trade offs made by the design team are worthy of study, as they run contrary to accepted wisdom.

VIA C3

Main article: VIA C3

• Because memory performance is the limiting factor in many benchmarks, VIA processors implement large primary caches, large TLBs, and aggressive prefetching, among other enhancements. The VIA C3 is a family of X86 Central processing units for Personal computers designed by Centaur Technology and sold by VIA Technologies A Translation lookaside buffer ( TLB) is a CPU cache that is used by memory management hardware to improve the speed of Virtual address While these features are not unique to VIA, memory access optimization is one area where they have not dropped features to save die space. In fact, generous primary caches (128K) have always been a distinctive hallmark of Centaur designs.

• Generally, clock frequency is favored over increasing instructions per cycle. Complex features such as out-of-order instruction execution are deliberately not implemented, because they impact the ability to increase the clock rate, require a lot of extra die space and power, and have little impact on performance in several common application scenarios.

• The pipeline is arranged to provide one-clock execution of the heavily used register–memory and memory–register forms of x86 instructions. Several frequently used instructions require fewer pipeline clocks than on other x86 processors.

• Infrequently used x86 instructions are implemented in microcode and emulated. Microprogramming (ie writing microcode) is a method that can be employed to implement Machine instructions in a CPU relatively easily often using less This saves die space and reduces power consumption. The impact upon the majority of real world application scenarios is minimized.

• These design principles are derivative from the original RISC advocates, who stated a smaller set of instructions, better optimized, would deliver faster overall CPU performance. The C3 design cannot be considered a RISC design because it uses the x86's CISC instruction set for compatibility.

VIA C7

Main article: VIA C7

• VIA C7 Esther (C5J) as an evolutionary step after VIA C3 Nehemiah+ (C5P), in which Centaur followed their traditional approach of balancing performance against a constrained transistor / power budget. The VIA C7 is an X86 Central processing unit designed by Centaur Technology and sold by VIA Technologies.

• The cornerstone of the VIA C3 series chips' design philosophy has been that even a relatively simple in-order scalar core can offer reasonable performance against a complex superscalar out-of-order core if supported by an efficient "front-end", i. e. prefetch, cache and branch prediction mechanisms.

• In the case of VIA C7, the design team have focused on further streamlining the "front-end" of the chip, i. e. cache size, associativity and throughput as well as the prefetch system. ^[1] At the same time no significant changes to the execution core ("back-end") of the chip seem to have been made.

• The VIA C7 successfully further closes the gap in performance with AMD / Intel chips, since clock speed is not thermally constrained.

Comparative die size

Processor	Secondary Cache (k)	Die size 130 nm (mm²)	Die size 90 nm (mm²)
VIA C3 / VIA C7	64/128	52	30
Athlon XP	256	84	N/A
Athlon 64	512	144	84
Pentium M	2048	N/A	84
P4 Northwood	512	146	N/A
P4 Prescott	1024	N/A	110

NOTE: Even the 180 nm Duron Morgan core (106 mm²) with a mere 64 K secondary cache, when shrunk down to a 130 nm process, would have still had a die size of 76 mm². The AMD Duron was an X86 -compatible Computer processor manufactured by AMD. The VIA x86 core is clearly the smallest and cheapest to produce. As can be seen in this table, almost four C7 cores could be manufactured for the same cost as a single core P4 Prescott on 90 nm process; this because it costs about the same amount to manufacture a given surface area for most types of chip - with just over a quarter of the surface area of a Prescott P4, the VIA C7 costs around a quarter as much to manufacture. The Pentium 4 brand refers to Intel 's line of single- core mainstream desktop and Laptop Central processing units (CPUs introduced

References

External links

• Home page

---

© 2009 citizendia.org; parts available under the terms of GNU Free Documentation License, from http://en.wikipedia.org
Dapyx Software network: MP3 Explorer | Ebook Manager | Zenithic