The ARM architecture (previously, the Advanced RISC Machine, and prior to that Acorn RISC Machine) is a 32-bit RISC processor architecture developed by ARM Limited that is widely used in a number of embedded designs. The range of Integer values that can be stored in 32 bits is 0 through 4294967295 or −2147483648 through 2147483647 using Two's complement encoding An embedded system is a special-purpose Computer system designed to perform one or a few dedicated functions often with Real-time computing constraints Because of their power saving features, ARM CPUs are dominant in the mobile electronics market, where low power consumption is a critical design goal. In Electrical engineering, power consumption often refers to the Electrical energy over Time supplied to operate an Electrical appliance, although

Today, the ARM family accounts for approximately 75% of all embedded 32-bit RISC CPUs,^[1] making it one of the most widely used 32-bit architectures in the world. ARM CPUs are found in all corners of consumer electronics, from portable devices (PDAs, mobile phones, media players, handheld gaming units, and calculators) to computer peripherals (hard drives, desktop routers). A calculator is device for performing mathematical calculations distinguished from a Computer by having a limited problem solving ability and an interface optimized for interactive A hard disk drive ( HDD) commonly referred to as a hard drive, hard disk, or fixed disk drive, is a Non-volatile storage device A router ('rautər in the USA 'rutər in the UK and Ireland, or either pronunciation in Australia and Canada is a Computer whose software and hardware are usually Important branches in this family include Marvell's XScale and the Texas Instruments OMAP series. Marvell ( is an American producer of Storage, communications and consumer Semiconductor products The XScale, a microprocessor core, is Marvell 's (formerly Intel 's implementation of the fifth generation of the ARM architecture, and consists Texas Instruments ( better known in the electronics industry (and popularly as TI, is an American company based in Dallas, Texas, USA Texas Instruments OMAP (Open Multimedia Application Platform is a Texas Instruments proprietary Microprocessor for Multimedia applications,

History

A Conexant ARM processor used mainly in routers

The ARM design was started in 1983 as a development project at Acorn Computers Ltd. Please wikify (format this article or section as suggested in the Guide to layout and the Manual of Style A router ('rautər in the USA 'rutər in the UK and Ireland, or either pronunciation in Australia and Canada is a Computer whose software and hardware are usually Acorn Computers was a British Computer company established in Cambridge, England, in 1978

The team, led by Roger Wilson and Steve Furber, started development of a compact RISC CPU. Sophie Wilson, formerly Roger Wilson, is a British Computer scientist. Professor Stephen Byram Furber CBE, FRS, FREng (born 1953 in Manchester, England is the ICL Professor of Computer Engineering A key design goal was achieving low-latency input/output (interrupt) handling like the MOS Technology 6502 used in Acorn existing computer designs. The MOS Technology 6502 is an 8-bit Microprocessor that was designed by Chuck Peddle for MOS Technology in 1975 Acorn Computers was a British Computer company established in Cambridge, England, in 1978 Using the 6502 Acorn had managed to produce powerful, flexible, machines without resorting to costly direct memory access hardware. The MOS Technology 6502 is an 8-bit Microprocessor that was designed by Chuck Peddle for MOS Technology in 1975 A powerful chip that allowed the same style of design could represent a significant advantage for the company.

The team completed development samples called ARM1 by April 1985^[2], and the first "real" production systems as ARM2 the following year. The ARM2 featured a 32-bit data bus, a 32-bit address space, (although the program counter was limited to 26 bits as the top 6 bits served as the status flags), giving a 4 Gbyte address space, although only the first 64 Mbyte address range could be used for executing code, and sixteen 32-bit registers. In Computer architecture, a bus is a subsystem that transfers data between computer components inside a Computer or between computers In Computing, an address space defines a range of discrete addresses each of which may correspond to a physical or virtual Memory register, a network host The program counter, or shorter PC (also called the instruction pointer, part of the instruction sequencer in some Computers is a register in A gigabyte (derived from the SI prefix Giga-) is a unit of Information or Computer A megabyte is a unit of Information or Computer storage equal to either 106 (1000000 Bytes or 220 (1048576 bytes depending on In Computer architecture, a processor register is a small amount of storage available on the CPU whose contents can be accessed more quickly than storage One of these registers served as the (word aligned) program counter with its top 6 bits and lowest 2 bits holding the processor status flags. The program counter, or shorter PC (also called the instruction pointer, part of the instruction sequencer in some Computers is a register in In Computer programming, flag refers to one or more Bits that are used to store a binary value or Code that has an assigned meaning The ARM2 was possibly the simplest useful 32-bit microprocessor in the world, with only 30,000 transistors (compare with Motorola's six-year older 68000 model with around 70,000 transistors). In Electronics, a transistor is a Semiconductor device commonly used to amplify or switch electronic signals The Motorola 68000 is a 16/32-bit CISC Microprocessor core designed and marketed by Freescale Semiconductor (formerly Motorola Semiconductor Much of this simplicity comes from not having microcode (which represents about one-quarter to one-third of the 68000) and, like most CPUs of the day, not including any cache. Microprogramming (ie writing microcode) is a method that can be employed to implement Machine instructions in a CPU relatively easily often using less In Computer science, a cache (kæʃ like "cash") is a collection of data duplicating original This simplicity led to its low power usage, while performing better than the Intel 80286^[3]. The Intel 286, introduced on February 1, 1982, (originally named 80286, and also called iAPX 286 in the programmer's manual A successor, ARM3, was produced with a 4KB cache, which further improved performance.

In the late 1980s Apple Computer started working with Acorn on newer versions of the ARM core. Apple Inc, ( formerly Apple Computer Inc, is an American Multinational corporation with a focus on designing and manufacturing Consumer electronics Acorn Computers was a British Computer company established in Cambridge, England, in 1978 The work was so important that Acorn spun off the design team in 1990 into a new company called Advanced RISC Machines Ltd.. Acorn Computers was a British Computer company established in Cambridge, England, in 1978 For this reason, ARM is sometimes expanded as Advanced RISC Machine instead of Acorn RISC Machine. Acorn Computers was a British Computer company established in Cambridge, England, in 1978 Advanced RISC Machines became ARM Ltd when its parent company, ARM Holdings plc, floated on the London Stock Exchange and NASDAQ in 1998. The London Stock Exchange or LSE is a Stock exchange located in London, England. The NASDAQ (acronym of National Association of Securities Dealers Automated Quotations) is an American Stock exchange. [1]

This work would eventually turn into the ARM6. The first models were released in 1991, and Apple used the ARM6-based ARM 610 as the basis for their Apple Newton PDA. The Apple Newton, or simply Newton, is the IPhone 's predecessor and was an early line of Personal digital assistants developed and marketed by In 1994, Acorn used the ARM 610 as the main CPU in their Risc PC computers. Acorn Computers was a British Computer company established in Cambridge, England, in 1978 The Risc PC (codenamed Medusa) was Acorn Computers 's next generation RISC OS / Acorn RISC Machine computer launched in 1994

The core has remained largely the same size throughout these changes. ARM2 had 30,000 transistors, while the ARM6 grew to only 35,000. The idea is that the Original Design Manufacturer combines the ARM core with a number of optional parts to produce a complete CPU, one that can be built on old semiconductor fabs and still deliver substantial performance at a low cost. An original design manufacturer ( ODM) is a company which manufactures a product which ultimately will be branded by another firm for sale In the Microelectronics industry a semiconductor fabrication plant (commonly called a fab) is a factory where devices such as Integrated circuits are manufactured

ARM's business has always been to sell IP cores, which licensees use to create microcontrollers and CPUs based on this core. In Electronic design a Semiconductor intellectual property core, IP block, IP core, or logic core is a reusable unit of logic cell A microcontroller (also MCU or µC is a functional Computer system-on-a- chip. The most successful implementation has been the ARM7TDMI with hundreds of millions sold in almost every kind of microcontroller equipped device. The ARM7TDMI processor is a 32-bit RISC CPU designed by ARM, and licensed for manufacture by an array of Semiconductor companies

DEC licensed the architecture (which caused some confusion because they also produced the DEC Alpha) and produced the StrongARM. Digital Equipment Corporation was a pioneering American company in the Computer industry Alpha, originally known as Alpha AXP, was a 64-bit Reduced instruction set computer (RISC Instruction set architecture (ISA developed The StrongARM Microprocessor is a faster version of the Advanced RISC Machines ARM design At 233 MHz this CPU drew only 1 watt of power (more recent versions draw far less). The watt (symbol W) is the SI derived unit of power, equal to one Joule of energy per Second. This work was later passed to Intel as a part of a lawsuit settlement, and Intel took the opportunity to supplement their aging i960 line with the StrongARM. Intel 's i960 (or 80960) was a RISC -based Microprocessor design that became popular during the early 1990s as an embedded Intel later developed its own high performance implementation known as XScale which it has since sold to Marvell. The XScale, a microprocessor core, is Marvell 's (formerly Intel 's implementation of the fifth generation of the ARM architecture, and consists Marvell ( is an American producer of Storage, communications and consumer Semiconductor products

The common architecture supported on smartphones, Personal Digital Assistants and other handheld devices is ARMv4. A smartphone is a Mobile phone offering advanced capabilities beyond a typical mobile phone often with PC -like functionality A mobile device (also known as cellphone device, handheld device, handheld computer, "Palmtop" or simply handheld) is a pocket-sized XScale and ARM926 processors are ARMv5TE, and are now more numerous in high-end devices than the StrongARM, ARM925T and ARM7TDMI based ARMv4 processors. The XScale, a microprocessor core, is Marvell 's (formerly Intel 's implementation of the fifth generation of the ARM architecture, and consists The StrongARM Microprocessor is a faster version of the Advanced RISC Machines ARM design The ARM7TDMI processor is a 32-bit RISC CPU designed by ARM, and licensed for manufacture by an array of Semiconductor companies

http://www.arm.com/news/19720.html - 22 January 2008 - ARM Achieves 10 Billion Processor Milestone - Annual run rate now three billion processor shipments across very diverse markets.

ARM cores

Design notes

To keep the design clean, simple and fast, it was hardwired without microcode, like the much simpler 8-bit 6502 processor used in prior Acorn microcomputers. Microprogramming (ie writing microcode) is a method that can be employed to implement Machine instructions in a CPU relatively easily often using less The MOS Technology 6502 is an 8-bit Microprocessor that was designed by Chuck Peddle for MOS Technology in 1975 Acorn Computers was a British Computer company established in Cambridge, England, in 1978

The ARM architecture includes the following RISC features:

• Load/store architecture
• No support for misaligned memory accesses (now supported in ARMv6 cores)
• Orthogonal instruction set
• Large 16 × 32-bit register file
• Fixed instruction width of 32 bits to ease decoding and pipelining, at the cost of decreased code density. Orthogonal instruction set is a term used in Computer engineering. A register file is an array of Processor registers in a central processing unit (CPU. In Computing, a pipeline is a set of data processing elements connected in series so that the output of one element is the input of the next one (Later, "Thumb mode" increased code density. )
• Mostly single-cycle execution

To compensate for the simpler design, compared with contemporary processors like the Intel 80286 and Motorola 68020, some unique design features were used:

• Conditional execution of most instructions, reducing branch overhead and compensating for the lack of a branch predictor
• Arithmetic instructions alter condition codes only when desired
• 32-bit barrel shifter which can be used without performance penalty with most arithmetic instructions and address calculations
• Powerful indexed addressing modes
• A link register for fast leaf function calls. The Intel 286, introduced on February 1, 1982, (originally named 80286, and also called iAPX 286 in the programmer's manual The Motorola 68020 is a 32-bit Microprocessor from Motorola, released in 1984. In Computer architecture, a branch predictor is the part of a processor that determines whether a Conditional branch in the instruction A status register (also flag register or condition code register (CCR) is a collection of flag Bits for a processor. A barrel shifter is a Digital circuit that can shift a data word by a specified number of Bits in one Clock cycle. Addressing modes are an aspect of the Instruction set architecture in most Central processing unit (CPU designs A link register, in many CPU architectures such as the PowerPC, ARM, and the PA-RISC, is a special purpose register which holds
• Simple, but fast, 2-priority-level interrupt subsystem with switched register banks

An interesting addition to the ARM design is the use of a 4-bit condition code on the front of every instruction, meaning that execution of every instruction is optionally conditional. In Computing, an interrupt is an asynchronous signal from hardware indicating the need for attention or a synchronous event in software indicating the need for a change Other CPU architectures typically only have condition codes on branch instructions.

This cuts down significantly on the encoding bits available for displacements in memory access instructions, but on the other hand it avoids branch instructions when generating code for small if statements. In Computer science, conditional statements, conditional expressions and conditional constructs are features of a Programming language which The standard example of this is the Euclidean algorithm:

In the C programming language, the loop is:

int gcd (int i, int j)  {    while (i != j)    {        if (i > j)            i -= j;       else            j -= i;    }    return i; }

In ARM assembly, the loop is:

loop    CMP    Ri, Rj       ; set condition "NE" if (i != j)                            ;               "GT" if (i > j),                             ;            or "LT" if (i < j)                   SUBGT  Ri, Ri, Rj   ; if "GT", i = i-j;          SUBLT  Rj, Rj, Ri   ; if "LT", j = j-i;         BNE    loop         ; if "NE", then loop

which avoids the branches around the then and else clauses. In Number theory, the Euclidean algorithm (also called Euclid's algorithm) is an Algorithm to determine the Greatest common divisor (GCD tags please moot on the talk page first! --> In Computing, C is a general-purpose cross-platform block structured See the terminology section below for information regarding inconsistent use of the terms assembly and assembler

Another unique feature of the instruction set is the ability to fold shifts and rotates into the "data processing" (arithmetic, logical, and register-register move) instructions, so that, for example, the C statement

a += (j << 2);

could be rendered as a single word, single cycle instruction on the ARM.

ADD Ra, Ra, Rj, LSL #2

This results in the typical ARM program being denser than expected with less memory access; thus the pipeline is used more efficiently. Even though the ARM runs at what many would consider to be low speeds, it nevertheless competes quite well with much more complex CPU designs.

The ARM processor also has some features rarely seen on other RISC architectures, such as PC-relative addressing (indeed, on the ARM the PC is one of its 16 registers) and pre- and post-increment addressing modes. The program counter, or shorter PC (also called the instruction pointer, part of the instruction sequencer in some Computers is a register in The program counter, or shorter PC (also called the instruction pointer, part of the instruction sequencer in some Computers is a register in

Another item of note is that the ARM has been around for a while, with the instruction set increasing somewhat over time. Some early ARM processors (prior to ARM7TDMI), for example, have no instruction to store a two-byte quantity, thus, strictly speaking, for them it's not possible to generate code that would behave the way one would expect for C objects of type "volatile short".

The ARM7 and earlier designs have a three stage pipeline; the stages being fetch, decode, and execute. Higher performance designs, such as the ARM9, have a five stage pipeline. Additional changes for higher performance include a faster adder, and more extensive branch prediction logic.

The architecture provides a non-intrusive way of extending the instruction set using "coprocessors" which can be addressed using MCR, MRC, MRRC and MCRR commands from software. The coprocessor space is divided logically into 16 coprocessors with numbers from 0 to 15, coprocessor 15 (cp15) being reserved for some typical control functions like managing the caches and MMU operation (on processors that have one). A memory management unit ( MMU) sometimes called paged memory management unit ( PMMU) is a Computer hardware component responsible for handling

In ARM based machines, peripheral devices are usually attached to the processor by mapping their physical registers into ARM memory space or into the coprocessor space or connecting to another device (a bus) which in turn attaches to the processor. Coprocessor accesses have lower latency so some peripherals (for example XScale interrupt controller) are designed to be accessible in both ways (through memory and through coprocessors). The XScale, a microprocessor core, is Marvell 's (formerly Intel 's implementation of the fifth generation of the ARM architecture, and consists

Thumb

To improve compiled code-density, processors since the ARM7TDMI have featured the Thumb mode. When in this mode, the processor executes 16-bit instructions. Most of these 16-bit-wide Thumb instructions are directly mapped to normal ARM instructions. The space-saving comes from making some of the instruction operands implicit and limiting the number of possibilities compared to the full ARM mode instruction.

In Thumb, the smaller opcodes have less functionality. For example, only branches can be conditional, and many opcodes are restricted to accessing only half of all of the CPU's general purpose registers. The shorter opcodes give improved code density overall, even though some operations require extra instructions. In situations where the memory port or bus width is constrained to less than 32 bits, the shorter Thumb opcodes allow increased performance compared with 32-bit ARM code, as less program code may need to be loaded into the processor over the constrained memory bandwidth.

Embedded hardware, such as the Game Boy Advance, typically have a small amount of RAM accessible with a full 32-bit datapath; the majority is accessed via a 16 bit or narrower secondary datapath. The Game Boy Advance (often shortened to GBA) is a 32-bit handheld video game console developed manufactured and marketed by Nintendo. In this situation, it usually makes sense to compile Thumb code and hand-optimise a few of the most CPU-intensive sections using full 32-bit ARM instructions, placing these wider instruction into the 32-bit bus accessible memory.

The first processor with a Thumb instruction decoder was the ARM7TDMI. All ARM9 and later families, including XScale have included a Thumb instruction decoder. The XScale, a microprocessor core, is Marvell 's (formerly Intel 's implementation of the fifth generation of the ARM architecture, and consists

DSP Enhancement Instructions

To improve the ARM architecture for digital signal processing and multimedia applications, a few new instructions were added to the set [5]. Digital signal processing ( DSP) is concerned with the representation of the signals by a sequence of numbers or symbols and the processing of these signals These seem to be signified by an "E" in the name of the ARMv5TE and ARMv5TEJ architectures.

The new instructions are common in digital signal processor architectures. A digital signal processor ( DSP or DSP micro) is a specialized Microprocessor designed specifically for Digital signal processing, generally They are variations on signed multiply-accumulate, saturated add and subtract, and count leading zeros.

Jazelle

A technology called Jazelle DBX (Direct Bytecode eXecution) allows recent ARM architectures to execute some Java bytecode in hardware as a third execution state alongside the existing ARM and Thumb modes. Java bytecode is the form of instructions that the Java virtual machine executes

The most prominent use of Jazelle is by manufacturers of mobile phones to increase the execution speed of Java ME games and applications. In computing the Java Platform Micro Edition or Java ME (still commonly referred to by its previous name Java 2 Platform Micro Edition or J2ME) is a specification

A Jazelle-aware Java Virtual Machine (JVM) will attempt to run Java bytecodes in hardware, whilst returning to the software for more complicated, or lesser-used bytecode operations. A Java Virtual Machine ( JVM) is a set of computer software programs and data structures which use a Virtual machine ARM claim that approximately 95% of bytecode in typical program usage ends up being directly processed in the hardware.

Jazelle functionality was specified in the ARMv5TEJ architecture^[11] and the first processor with Jazelle technology was the ARM926EJ-S^[12]: Jazelle is denoted by a 'J' appended to the CPU name.

The published specifications are very incomplete, being only sufficient for writing operating system code that can support a JVM that uses Jazelle. An operating system (commonly abbreviated OS and O/S) is the software component of a Computer system that is responsible for the management and coordination The declared intent is that only the JVM software needs to (or is allowed to) depend on the hardware interface details. This tight binding facilitates that the hardware and JVM can evolve together without affecting other software. In effect, this gives ARM Ltd. considerable control over which JVMs are able to exploit Jazelle.

Implementation

The Jazelle extension is implemented as an extra stage between the fetch and decode stages in the processor pipeline. Recognised bytecodes are converted into a string of one or more native ARM instructions.

The Jazelle mode moves JVM interpretation into hardware for the most common simple JVM instructions. This is intended to significantly reduce the cost of interpretation. Among other things, this reduces the need for JIT and other JVM accelerating techniques^[13]. JVM instructions that are not implemented in Jazelle hardware cause appropriate routines in the Jazelle-aware JVM implementation to be invoked. Details are not published.

Jazelle mode is entered via the BXJ instructions. A hardware implementation of Jazelle will only cover a subset of JVM bytecodes. For unhandled bytecodes—or if overridden by the operating system—the hardware will invoke the software JVM. The system is designed so that the software JVM does not need to know which bytecodes are implemented in hardware and a software fallback is provided by the software JVM for the full set of bytecodes.

Instruction set

The instruction set used in Jazelle mode is documented—it is Java bytecode after all. An instruction set is a list of all the instructions and all their variations that a processor can execute Java bytecode is the form of instructions that the Java virtual machine executes However, ARM have chosen to remain quiet on the exact execution environment details; the documentation provided with Sun's HotSpot Java Virtual Machine goes as far as to state: For the avoidance of doubt, distribution of products containing software code to exercise the BXJ instruction and enable the use of the ARM Jazelle architecture extension without [. HotSpot is the primary Java Virtual Machine for desktops and servers produced by Sun Microsystems. A Java Virtual Machine ( JVM) is a set of computer software programs and data structures which use a Virtual machine . ] agreement from ARM is expressly forbidden. ^[14].

Employees of ARM have in the past published several white papers that do give some good pointers about the processor extension. A white paper is an authoritative report or guide that often addresses problems and how to solve them Versions of the ARM Architecture Reference Manual available from 2008 have included pseudocode for the 'BXJ' (Branch and eXchange to Java) instruction, but with the finer details being shown as "SUB-ARCHITECTURE DEFINED" and documented elsewhere. Pseudocode is a compact and informal high-level description of a Computer programming Algorithm that uses the structural conventions of some Programming language

Application binary interface (ABI)

The Jazelle state relies on an agreed calling convention between the JVM and the Jazelle hardware state. In Computer science, a calling convention is a standardized method for a program to pass parameters to a function and receive a result value back from it This application binary interface is not published by ARM, rendering Jazelle an undocumented feature for most users and Free Software JVMs. In Computer software, an application binary interface ( ABI) describes the low-level interface between an application program and the Operating system Undocumented features are frequently found in Computer software releases

The entire VM state is held within normal ARM registers, allowing compatibility with existing operating systems and interrupt handlers unmodified. Restarting a bytecode (such as following a return from interrupt) will re-execute the complete sequence of related ARM instructions.

Specific registers are designated to hold the most important parts the JVM state, registers r0-r3 hold an alias of the top of the Java stack, r4 holds Java local operand zero (pointer to *this) and r6 contains the Java stack pointer. ^[15]

Jazelle reuses the existing Program Counter register r15^[16]. The program counter, or shorter PC (also called the instruction pointer, part of the instruction sequencer in some Computers is a register in A pointer to the next bytecode goes in r14^[17], so the use of the PC is not generally user-visible except during debugging.

CPSR: Mode indication

Java bytecode is indicated as the current instruction set by a combination of two-bits in the ARM CPSR (Current Program Status Register). The 'T'-bit must be cleared and the 'J'-bit set. ^[18]

Bytecodes are decoded by the hardware in two stages (versus a single stage for Thumb and ARM code) and switching between hardware and software decoding (Jazelle mode and ARM mode) takes ~4 clock cycles. ^[19].

For entry to Jazelle hardware state to succeed, the JE (Jazelle Enable)^[11] bit in the CP14:c0(c2)[bit 0] register must be set; clearing of the JE bit by a [privileged] operating-system provides a high-level override to prevent application programs from using the hardware Jazelle acceleration^[20], additionally the CV (Configuration Valid) bit^[11] found in CP14:c0(c1)[bit 1]^[20] must be set to show that there is a consistent Jazelle state setup for the hardware to use.

BXJ: Branch to Java

The BXJ instruction attempts to switch to Jazelle state, and if allowed and successful, sets the 'J' bit in the CPSR; otherwise "falling through" and acting as a standard BX (Branch) instruction. ^[11] The only time when an operating system, or debugger must be fully aware of the Jazelle mode is when decoding a faulted or trapped instruction. The Java PC pointing to the next instructions must be placed in the Link Register (r14) before executing the BXJ branch request, as regardless of hardware or software processing, the system must know where to begin decoding.

Because the current state is held in the CPSR, the bytecode instruction set is automatically reselected after task-switching and processing of the current Java bytecode is restarted. ^[15]

Following an entry into the Jazelle state mode, bytecodes can be processed in one of three ways; decoded and executed natively in hardware, handled in software (with optimised ARM/ThumbEE JVM code), or treated as an invalid/illegal opcode. The third case will cause a branch to an ARM exception mode, as will a Java bytecode of 0xff, which is used for setting JVM breakpoints^[21].

Execution will continue in hardware until an unhandled bytecode is encountered, or an exception occurs. Between 134 and 149 bytecodes (out of 203 bytecodes specified in the JVM specification) are translated and executed directly in the hardware.

Low-level registers

Low-level configuration registers, for the hardware virtual machine, are held in the ARM Co-processor "CP14 register c0" allowing detecting, enabling or disabling the hardware accelerator—if it is available. ^[22]

• The Jazelle Identity Register in register CP14:c0(c0) is read-only accessible in all modes.
• The Jazelle OS Control Register at CP14:c0(c1) is only accessible in kernel mode and will cause an exception when accessed in user-mode.
• The Jazelle Main Configuration Register at CP14:c0(c2) is write-only in user-mode and read-write in kernel mode.

A "trival" hardware implementation of Jazelle (as found in the QEMU emulator) is only required to support the BXJ opcode itself, treating BXJ as a normal BX instruction^[11] and to return RAZ (Read-As-Zero) for all of the CP14:c0 Jazelle-related registers^[23]. QEMU is a processor Emulator that relies on dynamic Binary translation to achieve a reasonable speed while being easy to port on new host CPU architectures

Thumb-2

Thumb-2 technology made its debut in the ARM1156 core, announced in 2003. Thumb-2 extends the limited 16-bit instruction set of Thumb with additional 32-bit instructions to give the instruction set more breadth. The resulting stated aim for Thumb-2 is to achieve code density similar to Thumb with performance similar to the ARM instruction set on 32-bit memory.

Thumb-2 also extends both the ARM and Thumb instruction set with yet more instructions, including bit-field manipulation, table branches, and conditional execution.

All ARMv7 chips support the Thumb-2 instruction set. Some chips, such as the Cortex-M3, support only the Thumb-2 instruction set. Other chips in the Cortex and ARM11 series support both "ARM instruction set mode" and "Thumb-2 instruction set mode" [6] [7] [8].

Thumb Execution Environment (ThumbEE)

ThumbEE, also known as Thumb-2EE, and marketed as Jazelle RCT (Runtime Compilation Target), was announced in 2005, first appearing in the Cortex-A8 processor. ThumbEE provides a small extension to the Thumb-2 extended Thumb instruction set, making the instruction set particularly suited to code generated at runtime (e. g. by JIT compilation) in managed Execution Environments. In Computing, just-in-time compilation ( JIT) also known as dynamic translation, is a technique for improving the runtime performance of a Computer ThumbEE is a target for languages such as Limbo, Java, C#, Perl and Python, and allows JIT compilers to output smaller compiled code without impacting performance. Limbo is a Programming language for writing distributed systems and is the language used to write applications for the Inferno Operating system C# (pronounced C Sharp is a Multi-paradigm NOTES FOR EDITORS "Perl" is not an acronym (read the "Name" section below Python is a general-purpose High-level programming language. Its design philosophy emphasizes programmer productivity and code readability In Computing, just-in-time compilation ( JIT) also known as dynamic translation, is a technique for improving the runtime performance of a Computer

New features provided by ThumbEE include automatic null pointer checks on every load and store instruction, an instruction to perform an array bounds check. Access to registers r8-r15 (where the Jazelle/DBX Java VM state is held) and the ability to branch to handlers—small sections of frequently called code—commonly used to implement a feature of a high level language, such as allocating memory for a new object.

Advanced SIMD (NEON)

The Advanced SIMD extension, marketed as NEON technology, is a combined 64 and 128 bit SIMD (Single Instruction Multiple Data) instruction set that provides standardized acceleration for media and signal processing applications. In Computing, SIMD ( S ingle I nstruction M ultiple D ata is a technique employed to achieve data level parallelism as in a Vector NEON can execute MP3 audio decoding on CPUs running at 10 MHz and can run the GSM AMR (Adaptive Multi-Rate) speech codec at no more than 13 MHz. GSM ( Global System for Mobile communications: originally from Groupe Spécial Mobile) is the most popular standard for Mobile phones in the A codec is a device or program capable of encoding and/or decoding a Digital Data stream or signal. It features a comprehensive instruction set, separate register files and independent execution hardware. NEON supports 8-, 16-, 32- and 64-bit integer and single precision floating-point data and operates in SIMD operations for handling audio/video processing as well as graphics and gaming processing. In Computing, SIMD ( S ingle I nstruction M ultiple D ata is a technique employed to achieve data level parallelism as in a Vector In NEON, the SIMD supports up to 16 operations at the same time.

VFP

VFP technology is a coprocessor extension to the ARM architecture. It provides low-cost single-precision and double-precision floating-point computation fully compliant with the ANSI/IEEE Std 754-1985 Standard for Binary Floating-Point Arithmetic. The IEEE Standard for Binary Floating-Point Arithmetic ( IEEE 754) is the most widely-used standard for floating-point computation and is followed by many VFP provides floating-point computation suitable for a wide spectrum of applications such as PDAs, smartphones, voice compression and decompression, three-dimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP architecture also supports execution of short vector instructions allowing SIMD (Single Instruction Multiple Data) parallelism. In Computing, SIMD ( S ingle I nstruction M ultiple D ata is a technique employed to achieve data level parallelism as in a Vector This is useful in graphics and signal-processing applications by reducing code size and increasing throughput.

Other floating-point and/or SIMD coprocessors found in ARM-based processors include FPA, FPE, iwMMXt. MMX is a single instruction multiple data (SIMD Instruction set designed by Intel, introduced in 1997 in their Pentium line of They provide some of the same functionality as VFP but are not opcode-compatible with it. In computer technology an opcode ( op eration code) is the portion of a Machine language instruction that specifies the operation to be performed

Security Extensions (TrustZone)

The Security Extensions, marketed as TrustZone(TM) Technology, is found in ARMv6KZ and later application profile architectures. It provides a low cost alternative to adding an additional dedicated security core to a SoC, by providing two virtual processors backed by hardware based access control. System-on-a-chip or system on chip ( SoC or SOC) refers to integrating all components of a Computer or other electronic System This enables the application core to switch between two states, referred to as worlds (to reduce confusion with other names for capability domains), in a manner such that information can be prevented from leaking from the more trusted world to the less trusted world. This world switch is generally orthogonal to all other capabilities of the processor and so each world can operate independently of the other while using the same core. Memory and peripherals are then made aware of the operating world of the core and may use this to provide access control to secrets and code on the device. A typical application of TrustZone Technology is to run a rich operating system in the less trusted world, and smaller security-specialized code in the more trusted world.

ARM licensees

ARM Ltd does not manufacture and sell CPU devices based on their own designs, but rather, licenses the processor architecture to interested parties. ARM offers a variety of licensing terms, varying in cost and deliverables. To all licensees, ARM provides an integratable hardware description of the ARM core, as well as complete software development toolset (compiler, debugger, SDK), and the right to sell manufactured silicon containing the ARM CPU. A compiler is a Computer program (or set of programs that translates text written in a computer language (the source language) into another A debugger is a Computer program that is used to test and Debug other programs A software development kit ( SDK or " devkit " is typically a set of development tools that allows a Software engineer to create applications Silicon (ˈsɪlɪkən or /ˈsɪlɪkɒn/ silicium is the Chemical element that has the symbol Si and Atomic number 14 Fabless licensees, who wish to integrate an ARM core into their own chip design, are usually only interested in acquiring a ready-to-manufacture verified IP core. In Electronic design a Semiconductor intellectual property core, IP block, IP core, or logic core is a reusable unit of logic cell For these customers, ARM delivers a gate netlist description of the chosen ARM core, along with an abstracted simulation model and test programs to aid design integration and verification. More ambitious customers, including integrated device manufacturers (IDM) and foundry operators, choose to acquire the processor IP in synthesizable RTL (Verilog) form. In the Semiconductor and electronic design industry Verilog is a Hardware description language (HDL used to model electronic systems. With the synthesizable RTL, the customer has the ability to perform architectural level optimizations and extensions. This allows the designer to achieve exotic design goals not otherwise possible with an unmodified netlist (high clock speed, very low power consumption, instruction set extensions, etc. ). While ARM does not grant the licensee the right to resell the ARM architecture itself, licensees may freely sell manufactured product (chip devices, evaluation boards, complete systems, etc. ). Merchant foundries can be a special case; not only are they allowed to sell finished silicon containing ARM cores, they generally hold the right to remanufacture ARM cores for other customers. Merchants function as professionals who deal with Trade, dealing in commodities that they do not produce themselves in order to produce Profit. In the Microelectronics industry a semiconductor fabrication plant (commonly called a fab) is a factory where devices such as Integrated circuits are manufactured

Like most IP vendors, ARM prices its IP based on perceived value. In architectural terms, the lower performance ARM cores command a lower license cost than the higher performance cores. In terms of silicon implementation, a synthesizable core is more expensive than a hard macro (blackbox) core. Complicating price matters, a merchant foundry who holds an ARM license (such as Samsung and Fujitsu) can offer reduced licensing costs to its fab customers. In exchange for acquiring the ARM core through the foundry's in-house design services, the customer can reduce or eliminate payment of ARM's upfront license fee. Compared to dedicated semiconductor foundries (such as TSMC and UMC) without in-house design services, Fujitsu/Samsung charge 2 to 3 times more per manufactured wafer. Taiwan Semiconductor Manufacturing Company Limited ( Traditional Chinese: 台灣積體電路製造股份有限公司 abbrev UMC ( United Microelectronics Corporation) was founded as Taiwan's first Semiconductor company in 1980 as a spin-off of the government-sponsored institute ITRI For low to mid volume applications, a design service foundry offers lower overall pricing (through subsidization of the license fee). For high volume mass produced parts, the long term cost reduction achievable through lower wafer pricing reduces the impact of ARM's NRE (Non-Recurring Engineering) costs, making the dedicated foundry a better choice.

Many semiconductor or IC design firms hold ARM licenses: Analog Devices, Atmel, Broadcom, Cirrus Logic, Faraday technology, Freescale (spun off from Motorola in 2004), Fujitsu, Intel (through its settlement with Digital Equipment Corporation), IBM, Infineon Technologies, Nintendo, NXP Semiconductors (spun off from Philips in 2006), OKI, Samsung, Sharp, STMicroelectronics, Texas Instruments and VLSI are some of the many companies who have licensed the ARM in one form or another. Analog Devices ( is an American multinational producer of Semiconductor devices } Atmel Corporation ( is a manufacturer of Semiconductors, founded in 1984. Broadcom Corporation is an American supplier of Integrated circuits (ICs for broadband communications Cirrus Logic ( is a fabless semiconductor supplier specializing in analog mixed-signal and DSP chips Freescale Semiconductor Inc is an American Semiconductor manufacturer Motorola Inc ( is an American, multinational Fortune 100, Telecommunications company based in Schaumburg Illinois. is a Japanese company specializing in Semiconductors Computers ( Supercomputers Personal computers, servers, Telecommunications Digital Equipment Corporation was a pioneering American company in the Computer industry International Business Machines Corporation abbreviated IBM and nicknamed "Big Blue", is a multinational Computer Technology Infineon Technologies AG () was founded in April 1999 when the Semiconductor operations of parent company Siemens AG, were spun off to form a separate is a Multinational corporation headquartered in Kyoto Japan founded on NXP (for Next eXPerience) Semiconductors is the name for the new Semiconductor company founded by Philips as announced by its CEO Frans Koninklijke Philips Electronics NV ( Royal Philips Electronics Inc. ( is a Japanese electronics company founded (as Meikosha Ltd in January 1881 by Kibataro Oki Samsung Electronics (SEC Hangul:삼성전자,,,) is the world's largest Consumer electronics company headquartered in Seocho Samsung Town in () is a Japanese Electronics manufacturer founded in 1912 It takes its name from one of its founder's first inventions the Ever-Sharp Mechanical pencil, which STMicroelectronics (,)is an franco-italian Electronics and Semiconductor manufacturer headquartered in in Geneva, Switzerland. Texas Instruments ( better known in the electronics industry (and popularly as TI, is an American company based in Dallas, Texas, USA VLSI Technology Inc was a company which designed and manufactured custom and semi-custom ICs The company was based in Silicon Valley, with headquarters at 1109 Although ARM's license terms are covered by NDA, within the IP industry, ARM is widely known to be among the most expensive CPU cores. A non-disclosure agreement (NDA also known as a confidentiality agreement, confidential disclosure agreement (CDA proprietary information agreement A single customer product containing a basic ARM core can incur a one-time license fee in excess of (USD) $200,000. Where significant quantity and architectural modification are involved, the license fee can exceed $10M.

ARM believes that its base of 200+ semiconductor licensees gives it a chance to succeed in the ongoing controversies regarding the use of ARM or Intel architectures in mobile computers.

Approximate licensing costs

ARM's 2006 annual report and accounts state that royalties totalling 88. 7 million GBP (164. 1 million USD) were the result of licensees shipping 2. 45 billion units^[24]. This is equivalent to 0. 036 GBP (0. 067 USD) per unit shipped. However, this is averaged across all cores, including expensive new cores and inexpensive older cores.

In the same year ARM's licensing revenues for processor cores were £65. 2 million ($119. 5 million)^[25], in a year when 65 processor licenses were signed^[26], an average of 1 million GBP (1. 84 million USD) per license. Again, this is averaged across both new and old cores.

Given that ARM's 2006 income from processor cores was approximately 60% from royalties and 40% from licenses, ARM makes the equivalent of 0. 06 GBP (0. 11 USD) per unit shipped including both royalties and licenses. However, as one-off licenses are typically bought for new technologies, unit sales (and hence royalties) are dominated by more established products. Hence, these figures above do not reflect the true costs of any single ARM product.

References

See also

• Inferno
• DirectBand
• AMULET - a family of asynchronous ARMs
• Philips LPC2000 ARM7TDMI-S Microcontrollers
• Texas Instruments OMAP - an ARM core plus DSP and application acceleration cores
• Armulator, ARM Instruction Set Simulator
• SkyEye simulator - an open source ARM Instruction Set Simulator

External links

• ARM Ltd.
• ARM Assembler Programming; tutorial, resources, and examples
• ARM architecture opcode map, for ARMv4T and ARMv5TE
• TrustZone(TM) Technology
• ARM Microcontroller Development Resources - header files, schematics, CAD files, etc. Events 558 - In Constantinople, the dome of the Hagia Sophia collapses Year 2007 ( MMVII) was a Common year starting on Monday of the Gregorian calendar in the 21st century. Inferno is an Operating system for creating and supporting distributed services DirectBand is a North American wireless datacast network owned and operated by Microsoft. AMULET is a series of microprocessors that implement the ARM processor architecture LPC2000 is a series of 32-bit Microcontrollers from NXP Semiconductors. Texas Instruments OMAP (Open Multimedia Application Platform is a Texas Instruments proprietary Microprocessor for Multimedia applications, ARM Instruction Set Simulator Armulator, is one of the software development tools provided by ARM Limited to all licensees of the ARM architecture. The table below compares basic information about Virtual machine (VM packages .
• Arm Architecture